D100 drone SoC system architecture
Pre-silicon architecture, DeepGrid Semi. Values are design targets. Select any block to trace its connections.
Select a block to see what it receives and feeds; the arrows show each connection.
INCameras · IMU, magnetometer, barometer · RC receiver and telemetry radio (external)
D100 package · 130 nm ASIC at 200 MHz
Flight control · hard real-time
DGridRiscV × 2RV32IM_Zicsr · FC core + NAV core · PX4 / ArduPilot loop
①IMU / MAG / BAROSPI × 3 · 8 kHz
④ESC OUTDShot600 · 8 channels
RC + telemetrySBUS · CRSF · MAVLink over UART
Visual-inertial odometry
②MIPI CSI-22 lanes · up to 1080p60
ISPrectify + LSC
FeatureFAST + BRIEF · 2k points per frame
③Pose engineEKF · IMU pre-integration · sliding-window BA · 30 Hz pose, 6-DoF
AI · variant 2 only · 28 nm die
NPUINT8 / INT4 · ~10 TOPS class · MAC array · SRAM 2 MB · DMA
YOLO-familyobject detection
SEGobstacle avoidance
AXI4 crossbar · 128-bit · 200 MHz
Failsafe island · isolated power and clock
⑤Link monitorRC loss · GPS loss · IMU fault · hardware, not firmware
FIndependent pathdirect to the ESCs · bypasses FC, VIO and AI
Safe-state FSMreturn-to-home / land
The failsafe path is independent of the mission stack.
Platform
LPDDR42 GB · 32-bit
eMMC / NANDlogging
PMU5 domains
SECsecure boot
ETH / USB3payload + ground link
CAN-FD × 2 · SPI · I²Cgimbal, payload
JTAGdebug
OUTESCs and motors (external)
PROTOTYPE Artix-7 FPGA · 81.25 MHz · validation onlyPRODUCT 130 nm ASIC · SkyWater SKY130 / IHP SG13G2 open PDK · 200 MHz fixed