DG32-LITE system architecture
Pre-silicon architecture, DeepGrid Semi. Values are design targets. Select any block to trace its connections.
Select a block to see what it receives and feeds; the arrows show each connection.
DG32-LITE · one 50 MHz clock domain · 130 nm CMOS · QFN-64
Safety core
④MAIN coreRV32IM · application
CHECKER coresame inputs, 2 cycles behind
Lockstep comparatorevery committed store
FFault latchfirst cause · FAULT_N
Memory and boot
Boot ROM 64 KBvalidates image, copies to SRAM
SRAM 32 KBdual-port: data + fetch
QSPI controllerboot flash + PSRAM window
DMAsecond bus master
Supervision
Windowed watchdog+ supply supervisor
Interrupt controller16 sources, both cores
On-chip bus · two masters (CPU, DMA) · deterministic latency · unmapped address → bus error, never a hang
Motor drive
①⑤3-phase PWMdead-time · hardware brake
DShot × 4
Timers × 2
System controlclock gates · pin mux
Sensing and math
②SAR ADC 8-bitdifferential · ~200 kSa/s
Encoder + Halledge timestamps
③CORDICsin · cos · atan2
Connectivity and test
UART × 2
SPIto 25 MHz
I²C100/400 kHz
GPIOatomic set/clear
JTAG + scan chainsproduction test
OUTOff-chip: QSPI NOR flash · gate driver + 3-phase bridge · motor sensors · host, sensors, test