SKU-1 BLDC motor controller system architecture

Pre-silicon architecture, DeepGrid Semi. Values are design targets. Select any block to trace its connections.

SYSTEM ARCHITECTURE · INTERACTIVESKU-1 BLDC motor controller system architecture

Select a block to see what it receives and feeds; the arrows show each connection.

INSpeed (rpm) · torque · halt · brake · ramp up / down (host commands)

SKU-1 · 130 nm BCD / high-voltage CMOS · 200 MHz

Host · control plane

①DGridRiscVcustom 32-bit RISC-V · 200 MHz
Timers · WDT · CCU
SRAM32 KB, up to 256 KB
ReRAM256 KB, up to 1 MB
Host interfacesI²C slave · UART × 4 · SPI · CAN-FD × 2 · JTAG

Mixed signal

16-bit ADCphase / bus / temp
DAC × 4reference out
Temp senseon-die, −40 to +125 °C
CSA × 3current-sense amps

Power path

B-B converterbuck-boost, PWM-pin driven
PWM × 7up to 200 kHz · 6 bridge + 1 aux
③FPre-drivers R / Y / B3 half-bridges · clock gating per phase
Star / deltawinding configuration, runtime selectable
Protectionthermal · overcurrent · overvoltage → gate shutdown, latched

AXI bus · memory-mapped register file · 200 MHz

Field-oriented control datapath

④PID tunerhardware · <1 µs tuning latency
②Rect → polarCORDIC · magnitude + angle
d,q → 3-phaseinverse Park + Clarke
Sine / trapezoidlookup tables · sinusoidal or 6-step

Sensor + feedback

Hall / quad / encsensored or sensorless
Angle (ω)rotor position + speed
iR iY iB rebuildtransfer function
Instant currentamplify + digitise

PROTOTYPE Artix-7 FPGA · 81.25 MHz · validation onlyPRODUCT 130 nm ASIC · SkyWater SKY130 / IHP SG13G2 open PDK · 200 MHz fixed

  1. ① Speed, torque, halt and brake commands reach the host.
  2. ② The datapath turns the torque command into phase drive: PID, CORDIC, inverse Park and Clarke, waveform lookup.
  3. ③ PWM drives the three half-bridge pre-drivers.
  4. ④ Current and angle feedback closes the PID loop.
  5. F A thermal, overcurrent or overvoltage fault shuts the gates and latches.