SKU-2 smart-meter SoC system architecture

Pre-silicon architecture, DeepGrid Semi. Values are design targets. Select any block to trace its connections.

SYSTEM ARCHITECTURE · INTERACTIVESKU-2 smart-meter SoC system architecture

Select a block to see what it receives and feeds; the arrows show each connection.

INV / I sense · 6 channels

SKU-2 · 130 nm CMOS · 200 MHz

Metrology

①DG-AFE66-ch 24-bit delta-sigma
②DECIMsinc³ · OSR 256
③④METROP Q S · THD-15

Compute + security

DGridRiscVRV32IM_Zicsr
DMA4-ch
DG-SEAES-256 · SHA-256

Always-on

PMU + RTC32.768 kHz XTAL · brownout 2.0 V · <2 µW

AHB-Lite multilayer · 32-bit · 4 masters / 9 slaves · 200 MHz

Peripherals

RTCtamper log
Timercapture / compare
LCD4 × 40 seg
⑤UARTDLMS / COSEM
Tampercase · magnet
GPIOrelay + LED

  1. ① Six voltage and current channels enter the front end.
  2. ② The 24-bit samples decimate through sinc³ at OSR 256.
  3. ③ The metrology engine computes P, Q, S and THD.
  4. ④ Results cross the 32-bit bus to the core and DMA.
  5. ⑤ Readings leave on the DLMS/COSEM UART.