SKU-3 hi-rel power-management IC system architecture

Pre-silicon architecture, DeepGrid Semi. Values are design targets. Select any block to trace its connections.

SYSTEM ARCHITECTURE · INTERACTIVESKU-3 hi-rel power-management IC system architecture

Select a block to see what it receives and feeds; the arrows show each connection.

IN28 V aircraft bus

SKU-3 · 180 nm BCD production, 130 nm 20 V devices for prototyping

Input conditioning

①EMI + TVSCM choke + pi · clamp 36 V
Ideal diodereverse polarity · back-to-back LDMOS
Inrushsoft-start FET · dI/dt limited
UVLO + OVLO18 V / 34 V · hysteretic

Pre-regulator · synchronous buck

②⑤Error amptype-III comp · 60 dB DC
PWM comp+ slope comp · 500 kHz to 2 MHz
Gate driveradaptive dead-time · 20 ns non-overlap
Current sensesense-FET + amp · cycle-by-cycle limit
Power stageLDMOS half-bridge

Reference + bias

BandgapBrokaw cell · 1.20 V · 12 ppm/°C
TrimOTP 6-bit · one-time, post-package
BiasPTAT + CTAT
OscRC 8 MHz · ±2% trimmed

Rail generation

③Buck · 5 V2 A · soft-start ramp
Window monitorOV / UV · ±3% window
OC limitfoldback → PG
Buck · 3.3 V3 A · soft-start ramp
Window monitorOV / UV · ±3% window
OC limitfoldback → PG
LDO · 1.8 V500 mA · soft-start ramp
Window monitorOV / UV · ±3% window
OC limitfoldback → PG
LDO · 1.2 / 0.9 V300 mA · soft-start ramp
Window monitorOV / UV · ±3% window
OC limitfoldback → PG

Supervision · sequencing · telemetry

④Sequencerprogrammable 4-step order · FSM + delay counter · TMR
Telemetry10-bit SAR ADC · 500 kSPS · V / I / die temp · SPI
Watchdogwindowed · 1 ms / 10 ms
SEU hardenDICE latches · TMR on the FSM

  1. ① The 28 V bus enters input conditioning.
  2. ② The conditioned bus feeds the pre-regulator.
  3. ③ The pre-regulator output feeds the four rail regulators.
  4. ④ Each rail reports power-good to the sequencer through its window monitor and current limit.
  5. ⑤ Current sense closes the peak-current-mode inner loop.