SKU-5 interface transceiver system architecture

Pre-silicon architecture, DeepGrid Semi. Values are design targets. Select any block to trace its connections.

SYSTEM ARCHITECTURE · INTERACTIVESKU-5 interface transceiver system architecture

Select a block to see what it receives and feeds; the arrows show each connection.

SKU-5 · 130 nm with 5 V thick-oxide LDMOS

Channel 1 · RS-485 · half duplex · up to 256 nodes · −7 to +12 V CM

Logic IF1.8 V core · level shift to 5 V · TXD · RXD · EN/STB
①Pre-driverslew shaping · dV/dt 3 V/ns trimmed
②Output stagediff push-pull · thick-oxide 5 V LDMOS
Prot logicEN interlock · no bus contention
Faultthermal + short · 150 °C shutdown
④Receiverhysteresis comp · 30 mV hyst · 50 ns prop
Failsafe biasidle = recessive · open / short / idle
ESD + EMC±15 kV, rated per test standard
Local supply + osc3.3 V LDO + bandgap · 40 MHz ref

Bus pins

③A / BRS-485
CANH / CANLCAN-FD

Channel 2 · CAN-FD · 8 Mbps data · ISO 11898-2 · ±12 V CM

Local supply + osc3.3 V LDO + bandgap · 40 MHz · bit-time recovery
ESD + EMC±15 kV, rated per test standard
Failsafe biasidle = recessive · open / short / idle
Output stagediff push-pull · thick-oxide 5 V LDMOS
Pre-driverslew shaping · dV/dt 3 V/ns trimmed
Logic IF1.8 V core · level shift to 5 V · TXD · RXD · EN/STB
Receiverhysteresis comp · 30 mV hyst · 50 ns prop
Faultthermal + short · 150 °C shutdown
Prot logicTXD timeout · bus-fault detect

  1. ① TXD enters the logic interface and is level-shifted to 5 V.
  2. ② The pre-driver shapes the edge for the output stage.
  3. ③ The differential output drives the bus pins.
  4. ④ The receiver reads the bus back to RXD. Channel 2 follows the same path.