SKU-6 quad-rail voltage supervisor system architecture

Pre-silicon architecture, DeepGrid Semi. Values are design targets. Select any block to trace its connections.

SYSTEM ARCHITECTURE · INTERACTIVESKU-6 quad-rail voltage supervisor system architecture

Select a block to see what it receives and feeds; the arrows show each connection.

SKU-6 · 130 nm CMOS prototype, 180 nm production

Sense chain · one per rail

④VIN 15V0 · ESD 2 kV
①Dividerpoly R ladder · 0.1% match
Comparatorchopper-stabilised · ±1% · 8 mV hyst
Deglitchdigital counter · 8 µs
VIN 23V3 · ESD 2 kV
Dividerpoly R ladder · 0.1% match
Comparatorchopper-stabilised · ±1% · 8 mV hyst
Deglitchdigital counter · 8 µs
VIN 31V8 · ESD 2 kV
Dividerpoly R ladder · 0.1% match
Comparatorchopper-stabilised · ±2% · 8 mV hyst
Deglitchdigital counter · 8 µs
VIN 41.2 / 0.9 V adjustable · ESD 2 kV
Dividerpoly R ladder · 0.1% match
Comparatorchopper-stabilised · ±2% · 8 mV hyst
Deglitchdigital counter · 8 µs

Fault logic

②Fault matrixmaskable · latched · priority enc · mask reg · latch · I²C regs

Output stage

⑤RESET_Nopen-drain · 200 ms delay, trimmed
③FAULT_Nopen-drain · asserts before RESET_N
MR / manualpush-button in

Reference + timebase

Bandgapcurvature-corrected · 1.20 V · 10 ppm/°C · PTAT + CTAT
TrimOTP 5-bit · ±0.5% after trim
Osc1 MHz · ±2% over −40 to 125 °C · ref current

Watchdog

Window logicopen + close · 100 ms to 1.6 s
WDIkick input
Timeoutcounter → RESET_N

  1. ① Each rail enters through its divider.
  2. ② The comparator and deglitch counter report a confirmed fault to the matrix.
  3. ③ The matrix latches it and drives FAULT_N, then RESET_N.
  4. ④ The trimmed bandgap sets every comparator threshold.
  5. ⑤ A missed or early watchdog kick times out to RESET_N.