SKU-8 rugged display driver and TCON system architecture
Pre-silicon architecture, DeepGrid Semi. Values are design targets. Select any block to trace its connections.
Select a block to see what it receives and feeds; the arrows show each connection.
INLVDS · MIPI DSI · parallel RGB
SKU-8 · 130 nm high-voltage CMOS · 200 MHz
Video input
①LVDS RXdual link · 655 Mbps per lane · SXGA 1280 × 1024 @ 60 Hz
DSI RXfour-lane MIPI DSI
Line bufferdual-port SRAM · 4 lines × 1280 × 24 bit
Pixel pipeline
②De-gammainput linearise
Colour3 × 3 matrix + WP
Dithertemporal + spatial
Gamma LUT14-bit table · temperature feedback
Timing + test
TCONH/V timing gen · programmable porches
PLLpixel clock · 100 MHz
Test patterncolour bars
BIST + safetyframe-freeze detect
Control bus · SPI / I²C register file · 200 MHz
Column (source) drivers · high-voltage
③DAC bank10-bit, 1 per column · resistor-string + buffer
Output ampsrail-to-rail HV · 0 to 12 V swing, thick oxide
④Column outputs × 12803 sub-pixels × 1280 → 3,840 outputs · charge-sharing precharge
Row + backlight
⑤Gate driver IFrow scan · up to 24 V level shift
VCOMcommon electrode
BacklightPWM + LED string · local dimming, 8 zones
Ambientlight + temp sense
OUTTo the panel · source / gate / VCOM / LED
- ① Video arrives over LVDS, MIPI DSI or parallel RGB.
- ② The line buffer feeds the pixel pipeline, 24 bits per pixel.
- ③ Dithered pixels drive the column DACs.
- ④ High-voltage amplifiers drive the 3,840 column outputs.
- ⑤ The timing controller scans the rows through the gate driver.