Ten chips, five kinds of system

DeepGrid's portfolio by the systems it goes into. Open a chip for what it replaces and its annex sheet; DG32-LITE, the part on first silicon, opens into its diagnostic story and films.

10 of 10 chips

Concept render of an autonomous forklift in a warehouse aisle, its sensor beams sweeping the racks — Motors and drives · Application concept

Motors and drives

2 chips · 1 on first silicon

In a motor drive, one chip runs the motor and another can stop it safely. SKU-1 replaces the driver-plus-microcontroller pair in fans, appliances, EV two- and three-wheelers, robots and actuators. SKU-4, DG32-LITE, is the safety processor that supervises a motor and can shut it down.

Motors and drivesSKU-1

BLDC motor controller

Native 5–120 V motor drive with hardware PID and CORDIC field-oriented control.

Used for

Runs the motor: fans, appliances, EV two- and three-wheelers, robotics and actuator joints.

Node: 130 nm BCD
Made at: SkyWater (USA)
Status: FPGA-validated

Annex sheet 2 First multi-project wafer run, cycle 1.

Motors and drivesSKU-4

DG32-LITE safety microcontroller

Lockstep safety MCU: dual DGridRiscV at 2-cycle skew, fault latch under 2 cycles.

Used for

Supervises the motor: motor-safety supervision, robot joints, and the field-oriented-control processor beside SKU-1.
EV battery management, and braking and steering controllers. Braking and steering need CAN-FD, which is on the DG32 roadmap and not on DG32-LITE.
Flight-critical redundancy feeding the D100 roadmap.

Node: 130 nm CMOS
Made at: SkyWater (USA)
Status: First silicon

Open product 5 films · 30 diagnostic tasks

Concept render of a DeepGrid-liveried truck on a wet highway at dusk, a camera-mirror display beside the cab — Vehicles · Application concept

Vehicles

3 chips

In a vehicle, the chips sit at the edges: the battery, the brakes, the radar, the bus and the wiring zones. The central computer of a software-defined vehicle is a sub-10 nm problem and is explicitly not claimed. What mature nodes own is everything around it.

VehiclesSKU-5

RS-485 and CAN-FD transceiver

RS-485 and CAN-FD with ±15 kV HBM ESD, replacing discontinued parts.

Used for

The CAN-FD and RS-485 link at every node on the vehicle bus.
Ships with every node on every industrial bus, including harsh wiring harnesses.

Node: 130 nm HV
Made at: SkyWater (USA)
Status: Design only

Annex sheet 6 Cycle-2 wafer run.

VehiclesSKU-7

77 GHz 4D radar

77 GHz 4D MIMO radar front end, fabricated outside US export control.

Used for

DeepGrid’s own truck mirror-tower radar, and automotive emergency braking.
Defence perimeter and counter-drone radar.

Node: 0.13 µm SiGe BiCMOS
Made at: IHP (Germany)
Status: Design only

Annex sheet 8 IHP wafer run, FY28.

VehiclesSKU-9

Zonal gateway

Zonal gateway: 16 smart e-fuses and four-port Gigabit TSN, replacing relay boxes.

Used for

The zonal layer of a software-defined vehicle: gateway, smart inputs and outputs, and the safety and security edge.

Node: 130 nm + 180 nm
Made at: SkyWater (USA)
Status: Design only

Annex sheet 10

Concept render of a border surveillance tower seen from an operator cabin, with tracked targets on the glass — Defence, avionics and drones · Application concept

Defence, avionics and drones

3 chips

Defence, avionics and drones need screened parts, and a failsafe that does not depend on software. The drone SoC keeps a hardware failsafe island wired straight to the motor controllers, so a crashed or jammed mission stack can still land the airframe.

Defence, avionics and dronesSKU-3

High-reliability power IC

Sequenced avionics rails on a 28 V bus, DO-160G and NSG-5962.

Used for

The sequenced 28 V power rails of avionics and military-vehicle electronics.

Node: 180 nm BCD
Made at: SCL Mohali (India)
Status: Design only

Annex sheet 4 Prototype on 130 nm, then production at SCL 180 nm in India.

Defence, avionics and dronesSKU-8

Rugged display driver

Rugged cockpit display driver, 0–12 V column amplifiers with compensated gamma.

Used for

Rugged cockpit displays.
Industrial control panels, rail passenger displays and automotive instrument clusters.

Node: 130 nm HV CMOS
Made at: SkyWater (USA)
Status: Design only

Annex sheet 9 Cycle-3 wafer run.

Defence, avionics and dronesD100

D100 drone SoC

Tactical drone SoC with an independent hardware failsafe island wired to the ESCs.

Used for

Flight control and visual-inertial navigation for drones, with a hardware failsafe to the speed controllers. Navigation is geometric, so it survives GPS jamming.

Node: 130 nm + 28 nm, multi-die SiP
Made at: Separate track
Status: FPGA-validated

Annex sheet 11 Track B: scoped and funded separately from the nine SKUs.

Concept render of a row of electricity smart meters on a utility wall at dusk, one open to show its metrology board, a transformer beyond the doorway — Grid and metering · Application concept

Grid and metering

1 chip

For the national smart-meter rollout, one chip measures the power and records tampering. Tamper detection is a tender requirement, so the chip keeps an always-on clock domain that logs a magnet or an opened case while mains power is cut.

Grid and meteringSKU-2

Smart-meter SoC

Six-channel 24-bit metrology front end with an always-on sub-2 µW RTC domain.

Used for

Class 0.5S metrology for electricity meters, with tamper logging on backup power.

Node: 130 nm CMOS
Made at: SkyWater (USA)
Status: FPGA-validated

Annex sheet 3 Cycle-1 wafer run, alongside SKU-1.

Concept render of an industrial controller board with a row of voltage regulators and a small supervisor chip beside them — On nearly every board · Application concept

On nearly every board

1 chip

Some parts go on nearly every circuit board, which is where the volume is. A supervisor watches a board’s power rails and a transceiver connects it to its bus. Neither is glamorous, and both ship with almost everything.

On nearly every boardSKU-6

Voltage supervisor

Four-rail supervisor with an 8 µs deglitch filter; the simplest chip through qualification first.

Used for

Watches up to four power rails and latches a fault, on nearly every circuit board.

Node: 180 nm CMOS
Made at: SCL Mohali (India)
Status: FPGA-validated

Annex sheet 7 Cycle-1 or cycle-2 wafer run; the first chip planned through MIL-883 qualification.

Where each chip goes is from the SKU Architecture Compendium (Technical Annex v3). Only DG32-LITE is on first silicon; the rest are architecture sheets with their wafer runs planned. Concept renders show where a product is used, not the product.

Motors and drives, in depth

DG32-LITE is a safety microcontroller for motors and batteries, and it can watch the machine it controls.

In DeepGrid’s portfolio it is SKU-4, the safety MCU. It is built to take the socket a Microchip or Renesas functional-safety microcontroller holds today: the independent processor in a battery pack, a motor drive, a braking or steering controller, a robot joint or a drone’s redundant flight path, whose job is to catch a fault and shut the system down.

Because it already sits beside the motor, it can do a second job in its spare cycles: watch that motor for faults before they trip anything. A wearing bearing, a broken rotor bar, a pump running dry, a winding getting hot. That is what the thirty tasks on this page are, and every one fits on its single 50 MHz core with no accelerator and no second chip.

24 of the 30 run faster than 1 kHz. The slowest takes 10.3 ms and the largest needs 20 KB. The limit that actually binds is the sensor on the motor, not the chip, and this page says where.

SKU Architecture Compendium, Technical Annex v3, sheet 5 · DG32-AI use-case playbook, pages 1 and 3

It goes into five places, and each one has its own faults worth watching.

The sockets below are DeepGrid’s own, from the portfolio annex. Beside each are the tasks from this page that fit it. That pairing is ours: the annex names the sockets and the playbook costs the tasks, but neither document matches them up.

SKU Architecture Compendium, Technical Annex v3, sheet 5: “replaces Microchip/Renesas functional-safety MCU sockets”

EV battery management and motor-safety supervision
The independent processor that watches a battery pack or a drive and can shut it down. Lockstep cores and the FAULT_N pin are the supervision; the diagnostics add warning before a trip.
Braking and steering controllers
Drives where a wrong output is a safety event, so a silent CPU fault has to trip in hardware.
These need the CAN-FD vehicle bus, which is on the roadmap and not on DG32-LITE.
Robot joints
One controller per joint, running the motor loop and watching the gearbox and load behind it.
The motor-control processor beside a BLDC driver
The field-oriented-control processor next to SKU-1, DeepGrid’s BLDC motor controller for fans, appliances, EV two- and three-wheelers, robotics and actuator joints.
Flight-critical redundancy for the D100 drone programme
A second, independent safety processor beside the flight computer. DG32-LITE drives drone speed controllers directly through its four hardware DShot channels.

The annex describes the lockstep safety MCU as on an ISO 26262 ASIL-D path. That is a direction, not a certification: no functional-safety certification is claimed for DG32.

In a motor drive, control comes first. Diagnostics has to fit around it.

A drive switches its power transistors thousands of times a second, and one wrong switching edge can short the bridge. So anything else the processor does must never delay the control loop, and must never be the thing that decides to shut the motor down.

DG32 keeps those two jobs apart. A lockstepped pair of cores and a hardware fault pin hold the trip limits. The diagnostic models on this page only advise: they raise a score or a class, and the deterministic monitor keeps the final say.

Playbook, page 12 · DG32-LITE architecture film, slide 3

“Why build it this way? A motor drive switches power transistors thousands of times a second. If the CPU silently computes a wrong value, it writes a wrong PWM edge, and a wrong edge can short a bridge leg. Entry-level motor MCUs catch faults with watchdogs and periodic software self-test. Hardware lockstep has lived in automotive parts such as AURIX, S32K and Hercules.”
DG32-LITE architecture film · slide 3 · 1:01–1:32

Control costs a fixed amount of hardware time, so what is left is a known budget.

The expensive steps of motor control run in dedicated hardware, so one loop costs about 300 cycles at any loop rate. The diagnostics live in what remains, and the playbook sizes every task against four numbers.

Scalar throughput: 12.5 MMAC/s
Model budget: 16.5 KB
Free cycles: 82 %
Hardware help: CORDIC

The film and the playbook count different things. The film’s 4,700 cycles at 10 kHz are what is left after the hardware part of one loop; the playbook’s 82 % is what is left for diagnostics with the whole control loop running. The budget for one inference is 12.5 million multiply-accumulates a second divided by the rate: 12.5 thousand at 1 kHz.

Playbook, page 3 · DG32-LITE architecture film, slides 9 and 10

“Here is what one loop costs. The current sample takes one hundred seventy-seven cycles. Each CORDIC operation takes fifty-three to fifty-eight. The regulators cost about eight cycles per instruction. Together the hardware part is about three hundred cycles, and it is the same at every loop rate. At twenty kilohertz, that is twelve percent of the period. So the question becomes how much firmware fits. At ten kilohertz there are about forty-seven hundred cycles left: enough for a full current and speed loop with an observer. At twenty kilohertz, twenty-two hundred, enough for field-weakening. At fifty kilohertz, seven hundred, an inner current loop only. The simulated ceiling is about one hundred kilohertz.”
DG32-LITE architecture film · slide 9 · 4:00–4:51

On this core, small classical models beat neural networks, and the signal matters more than the model.

Without a multiply array, comparisons and table lookups are the cheap operations. A 100-tree random forest at depth 8 is about 800 comparisons and no multiplies. That is not a compromise: on the CWRU bearing benchmark a random forest over five features reaches 95.6 %, and a review of 42 papers finds support-vector machines at 95 to 100 % against deep methods at 97 to 100 %, statistically the same.

What moves accuracy is the signal. In a twelve-feature ranking study, features taken at the known fault frequency outscored raw statistics four to five times (225.9 against 51.8). So the cycles go to band selection and envelope demodulation first, and a larger model last.

Playbook, pages 4 to 6

The 17 models the thirty tasks use, of the 19 that fit. Inference cost only; feature extraction is costed separately.
Model	What it does	Cycles	Inference	Tasks
LDA	Primary classifier	128	0.00 ms	5
Random forest, 100×d8	Primary classifier	3,200	0.06 ms	4
Logistic regression	Primary classifier	128	0.00 ms	3
Gradient boosting, 200×d4	Primary classifier	3,200	0.06 ms	2
Mahalanobis score	Anomaly score, single scalar	4,096	0.08 ms	2
Extended Kalman filter	Observer: sensorless FOC, thermal	2,400	0.05 ms	2
MLP 32-16-8-4	Nonlinear classifier or regressor	2,688	0.05 ms	2
Isolation forest	Unlabelled anomaly detection	3,200	0.06 ms	1
One-class SVM	Anomaly detection with a decision boundary	12,800	0.26 ms	1
k-NN, 200 prototypes	Field-adaptable classifier	25,600	0.51 ms	1
Nearest centroid	On-device baselining, no backward pass	1,024	0.02 ms	1
Gaussian mixture	Regime identification	2,048	0.04 ms	1
HMM, 8 state	Sequence and state tracking	3,072	0.06 ms	1
MLP autoencoder	Unsupervised drift detection	22,016	0.44 ms	1
MLP 128-64-32-8	Regression at the dense-network ceiling	41,984	0.84 ms	1
GRU, 16 units	Short sequence modelling	147,456	2.95 ms	1
1D-CNN 8/16/32	Raw-waveform classification	512,000	10.24 ms	1

8 Rotating machinery

Bearings are the most common motor failure, and an accelerometer catches them.

Bearings account for 44 % of motor failures and are the weakest fault class for current-only sensing, so this family reads vibration. Features taken at the bearing’s own fault frequencies outrank raw statistics four to five times, so the classifier behind them stays small.

ISO 20816 severity zones · ISO 13373 vibration monitoring

Playbook, page 7 and page 11

Bearing fault classification
Inner race, outer race, ball and cage defects
Goes into: BLDC motor control
Signal
Accelerometer, ≥5 kHz bandwidth · envelope + FFT-256 + moments
Runs
Random forest, 100×d8
Cost
0.92 ms890 Hz below 1 kHz20 KB
Bearing severity trending
ISO 20816 zone A/B/C/D from broadband RMS velocity
Signal
Accelerometer · decimate + RMS
Runs
LDA
Cost
0.14 ms>1 kHz0.7 KB
Gearbox and gear-mesh faults
Tooth damage, mesh-frequency sideband growth
Goes into: Robot joints
Signal
Accelerometer, order-tracked on encoder · envelope + FFT-512 + moments
Runs
Random forest, 100×d8
Cost
1.69 ms480 Hz below 1 kHz20 KB
Pump cavitation and dry-run
Separates cavitation, dry running and normal load
Goes into: BLDC motor control
Signal
Phase current + pressure over SPI · FFT-256 + moments
Runs
Gradient boosting, 200×d4
Cost
0.82 ms>1 kHz12 KB
Fan and blower imbalance
Blade damage, 1× and 2× amplitude ratio
Goes into: BLDC motor control
Signal
Accelerometer + tachometer · FFT-256 + moments
Runs
LDA
Cost
0.76 ms>1 kHz0.7 KB
Compressor valve faults
Valve leakage and flutter against crank angle
Goes into: BLDC motor control
Signal
Accelerometer + crank reference · envelope + FFT-256
Runs
Random forest, 100×d8
Cost
0.78 ms>1 kHz20 KB
Belt slip and misalignment
Dual-encoder differential, or vibration harmonic ratio
Goes into: BLDC motor control
Signal
Dual encoder or accelerometer · FFT-256
Runs
Logistic regression
Cost
0.62 ms>1 kHz0.7 KB
Shaft misalignment and looseness
1×, 2×, 3× harmonic pattern
Signal
Accelerometer · FFT-256 + moments
Runs
Random forest, 100×d8
Cost
0.82 ms>1 kHz20 KB

8 Electrical and power

The phase current the drive already samples carries rotor and stator faults.

Motor current signature analysis looks for sidebands around the supply frequency. The FFT that would resolve them is 8 MB, so the playbook evaluates Goertzel filters at only the predicted sideband frequencies instead.

ISO 20958 motor current signature analysis

Playbook, page 8 and page 11

Broken rotor bar detection
Twice-slip-frequency sidebands, f₁(1±2ks)
Goes into: BLDC motor control
Needs a 12 to 16-bit converter, or analog gain ahead of it
Signal
Phase current, ≥12-bit with notch · Goertzel
Runs
LDA
Cost
0.13 ms>1 kHz0.7 KB
Air-gap eccentricity
f₁ ± m·f_r sidebands from mixed eccentricity
Needs a 12 to 16-bit converter, or analog gain ahead of it
Signal
Phase current, ≥12-bit · Goertzel
Runs
LDA
Cost
0.13 ms>1 kHz0.7 KB
Stator inter-turn short
Negative-sequence current index against baseline
Goes into: Battery and motor supervision
Needs a 12 to 16-bit converter, or analog gain ahead of it
Signal
Three-phase current + voltage · Park + RMS
Runs
Mahalanobis score
Cost
0.14 ms>1 kHz2 KB
Phase loss and current unbalance
Sequence-component imbalance
Goes into: Battery and motor supervision
Signal
Phase current, already sampled · Park
Runs
Logistic regression
Cost
<0.01 ms>1 kHz0.7 KB
Arc-fault and partial discharge
Early insulation breakdown signature
Signal
HF current transformer + envelope · envelope + FFT-256
Runs
One-class SVM
Cost
0.97 ms840 Hz below 1 kHz6.9 KB
Power-quality events
Sag, swell, harmonic distortion, flicker
Signal
Line voltage and current, 64 cycles · Goertzel
Runs
LDA
Cost
0.13 ms>1 kHz0.7 KB
Battery state-of-health
SoH and SoC from charge-cycle shape
Goes into: Battery and motor supervision
Signal
Slow V / I / T sequence · moments
Runs
MLP 32-16-8-4
Cost
0.19 ms>1 kHz0.7 KB
Winding thermal estimation
Virtual temperature sensor from current history
Goes into: Battery and motor supervision
Signal
Current history + ambient · RMS
Runs
Extended Kalman filter
Cost
0.11 ms>1 kHz2 KB

8 Control, motion and sensing

Most of these run on the sensors the drive already has.

Sensorless observation, plausibility checking, regime identification, anomaly scoring and duty tracking depend on relative change rather than small-signal resolution, so they need no added parts.

Playbook, page 9

Sensorless rotor position
EKF flux observer, removes the position sensor
Goes into: Braking and steering
Signal
Phase current, CORDIC- assisted · Park
Runs
Extended Kalman filter
Cost
0.05 ms>1 kHz2 KB
Learned sensor plausibility
Encoder vs Hall vs back-EMF consistency
Goes into: Braking and steering, Drone flight redundancy
Signal
Existing peripherals, no added BOM · Park
Runs
Nearest centroid
Cost
0.02 ms>1 kHz1 KB
Operating-mode classification
Which duty regime the machine is in
Goes into: Robot joints
Signal
Encoder, Hall, current, temperature · RMS
Runs
Gaussian mixture
Cost
0.10 ms>1 kHz2 KB
Duty-cycle and state tracking
Start counts, dwell times, regime transitions
Goes into: Robot joints
Signal
Existing peripherals
Runs
HMM, 8 state
Cost
0.06 ms>1 kHz2 KB
Adaptive friction compensation
Learned cogging and friction feedforward
Goes into: Robot joints
Signal
Encoder + current · Park
Runs
MLP 32-16-8-4
Cost
0.06 ms>1 kHz0.7 KB
Kickback and stall detection
Sudden load transient classification
Goes into: Braking and steering, Robot joints, Drone flight redundancy
Signal
Phase current · RMS
Runs
Gradient boosting, 200×d4
Cost
0.12 ms>1 kHz12 KB
Load estimation and torque ripple
Torque ripple harmonics from current
Goes into: Braking and steering
Signal
Phase current · FFT-256
Runs
Logistic regression
Cost
0.62 ms>1 kHz0.7 KB
Multivariate anomaly scoring
Single scalar novelty score, raised as an IRQ
Goes into: Battery and motor supervision, Drone flight redundancy
Signal
Any fused sensor set · moments
Runs
Mahalanobis score
Cost
0.22 ms>1 kHz2 KB

6 Slower-rate and sequence

Trend and forecasting tasks read hours of history, so they can run slower.

Remaining-useful-life regression works from 64 hourly feature snapshots. Three of the six tasks that run below 1 kHz are in this family.

Playbook, page 10

Remaining-useful-life regression
Trend extrapolation over long feature history
Signal
64 hourly feature snapshots
Runs
MLP 128-64-32-8
Cost
0.84 ms970 Hz below 1 kHz10.5 KB
Unsupervised drift detection
Reconstruction error against learned healthy manifold
Signal
Any fused sensor set · moments
Runs
MLP autoencoder
Cost
0.58 ms>1 kHz5.5 KB
Short-horizon forecasting
Predicts a slow process variable a few steps ahead
Signal
Any slow scalar, 64-step history
Runs
GRU, 16 units
Cost
2.95 ms270 Hz below 1 kHz1.6 KB
Raw-waveform fault classification
End-to-end from the sampled window, no hand features
Signal
Accelerometer or current · decimate
Runs
1D-CNN 8/16/32
Cost
10.32 ms79 Hz below 1 kHz14 KB
Novelty detection without labels
Isolation-forest outlier score
Signal
Any fused sensor set · moments
Runs
Isolation forest
Cost
0.20 ms>1 kHz8 KB
Per-machine baselining
On-device prototype update, no backward pass
Signal
Any fused sensor set · moments
Runs
k-NN, 200 prototypes
Cost
0.65 ms>1 kHz6.4 KB

Compute is not the limit. The sensors are.

Rotor-bar and eccentricity faults show up as sidebands 40 to 60 dB below the supply frequency. An 8-bit converter resolves 42 dB, so the whole diagnostic range sits at or under its noise floor. Broken rotor bar, air-gap eccentricity and stator inter-turn detection need a 12 to 16-bit converter, or analog suppression and gain ahead of it. The sidebands are also close together, so they need 30 to 100 seconds of record at steady load.

Add one accelerometerThe highest-value addition, because bearings are 44 % of motor failures. It needs at least 5 kHz of usable bandwidth, which many low-cost MEMS parts lack, and a stud mount rather than a magnet or adhesive.
Add three-phase current and voltageUnlocks stator inter-turn detection and instantaneous power analysis. It needs a multi-channel converter; the part has one differential channel today.
Works today, unchangedSensorless observation, plausibility checking, regime identification, anomaly scoring and duty tracking run on the sensing already present, because they read relative change.

Playbook, page 11 (ISO 13373-1, 13373-2, 20958) · DG32-LITE architecture film, slide 14

“Against the STM32G0, the entry-level incumbent, the comparison is honest. DG32 leads on hardware lockstep, native DShot, hardware CORDIC and the on-chip AI variant, with an open RISC-V core. The G0 leads clearly on its twelve-bit multi-channel ADC, embedded flash, USB and CAN-FD, and on production maturity.”
DG32-LITE architecture film · slide 14 · 6:13–6:41

DG32-2DOM adds an attention engine, on its own clock, for the models the scalar core runs slowly.

None of the thirty tasks needs it. An attention kernel at 64/32/32 is 0.26 million multiply-accumulates, about 21 ms in software on DG32-LITE: it fits, but slowly. DG32-2DOM keeps the same lockstep controller and adds an INT8 engine on a separate clock, behind bridges, so it can never hold up motor control.

So the line is simple. DG32-LITE covers the thirty tasks on this page. DG32-2DOM is for the next class of model, the kind an entry-level motor MCU can only run in software.

Playbook, page 3 · DG32-2DOM architecture film, slides 1 and 12

“DG32-2DOM is the attention variant of Deepgrid Semi's DG32-LITE motor-control chip. It keeps the dual-core lockstep controller and adds an INT8 attention engine on its own clock, so a drive can watch its own motor for faults. The design is complete and in physical trials. Every figure here is a post-route, simulated or analytic value, and each one is labelled.”
DG32-2DOM architecture film · slide 1 · 0:00–0:30

“What is it for? Catching a wearing bearing, or a drive that starts behaving oddly, without an extra processor on the board, because the motor controller watches its own motor. The STM32G0 can only run that kind of model in software, so a hardware engine sets DG32-2DOM apart. On the roadmap it runs alongside DG32-LITE's first silicon, with its design finished and undergoing physical trials.”
DG32-2DOM architecture film · slide 12 · 5:17–5:49

Every figure here is derived, not measured, and the classifier never holds the trip.

Every latency, memory figure and rate on this page is calculated: feature-extraction cycles plus model cycles, at 4 cycles per int8 multiply-accumulate, against 82 % of a 50 MHz core. That constant is back-solved from the design documents. No workload has been compiled for or measured on DG32-LITE, which has not completed place-and-route.

Accuracy needs the same care. Forty of forty-one reviewed bearing-benchmark studies used splits open to data leakage; on a leakage-free split one classifier fell from 85.8 % to 69.5 %. Expect 65 to 80 % on bearings the model has never seen. That is why the classifier advises and the lockstep monitor holds the trip.

Playbook, page 12 · DG32-LITE architecture film, slides 6 and 16

“This is the safety core. MAIN runs the application. CHECKER runs the same instructions two cycles later, on the same inputs, and the comparator checks every committed store. On a mismatch, the first cause is latched and FAULT_N goes low. Route that pin to the gate-driver enable, and the bridge turns off in hardware, without waiting for firmware.”
DG32-LITE architecture film · slide 6 · 2:33–2:59

“Three ideas to hold on to. The protection is built into the processor itself, not bolted on in software. The costly parts of motor control are dedicated hardware, so the price of one loop is fixed and known in advance. And the weaknesses are named, with fixes scheduled. None of this has yet been measured on silicon, and no functional-safety certification is claimed; bring-up is where the numbers become real.”
DG32-LITE architecture film · slide 16 · 7:14–7:43

Bring a failure mode and a sample rate. We will tell you whether it fits.

If your machine is not among these thirty, the method is the same: the fault, the sensor that sees it, the rate it needs, and the model that fits the budget.

Ask DeepGrid The use-case playbook, 12 pages The control headroom these run in What each kind of figure rests on

Pre-silicon. Figures are design values verified in simulation and static timing, not measurements on fabricated parts, unless marked otherwise.

BLDC motor controller

DG32-LITE safety microcontroller

RS-485 and CAN-FD transceiver

77 GHz 4D radar

Zonal gateway

High-reliability power IC

Rugged display driver

D100 drone SoC

Smart-meter SoC

Voltage supervisor

DG32-LITE is a safety microcontroller for motors and batteries, and it can watch the machine it controls.

It goes into five places, and each one has its own faults worth watching.

EV battery management and motor-safety supervision

Braking and steering controllers

Robot joints

The motor-control processor beside a BLDC driver

Flight-critical redundancy for the D100 drone programme

In a motor drive, control comes first. Diagnostics has to fit around it.

Control costs a fixed amount of hardware time, so what is left is a known budget.

On this core, small classical models beat neural networks, and the signal matters more than the model.

Bearings are the most common motor failure, and an accelerometer catches them.

Bearing fault classification

Bearing severity trending

Gearbox and gear-mesh faults

Pump cavitation and dry-run

Fan and blower imbalance

Compressor valve faults

Belt slip and misalignment

Shaft misalignment and looseness

The phase current the drive already samples carries rotor and stator faults.

Broken rotor bar detection

Air-gap eccentricity

Stator inter-turn short

Phase loss and current unbalance

Arc-fault and partial discharge

Power-quality events

Battery state-of-health

Winding thermal estimation

Most of these run on the sensors the drive already has.

Sensorless rotor position

Learned sensor plausibility

Operating-mode classification

Duty-cycle and state tracking

Adaptive friction compensation

Kickback and stall detection

Load estimation and torque ripple

Multivariate anomaly scoring

Trend and forecasting tasks read hours of history, so they can run slower.

Remaining-useful-life regression

Unsupervised drift detection

Short-horizon forecasting

Raw-waveform fault classification

Novelty detection without labels

Per-machine baselining

Compute is not the limit. The sensors are.

DG32-2DOM adds an attention engine, on its own clock, for the models the scalar core runs slowly.

Every figure here is derived, not measured, and the classifier never holds the trip.

Bring a failure mode and a sample rate. We will tell you whether it fits.