DG32 / MOTOR-CONTROL SILICON
DG32 puts a RISC-V control core, the motor-control peripherals and a hardware lockstep safety monitor on one 130 nm chip.
Pre-silicon: first silicon rides the September 2026 shuttle, and every figure on this site is a design value until bring-up.
ILLUSTRATIVE MODEL · NOT A MASK LAYOUT · DRAG TO ROTATE
Pre-silicon figures.
Design values, not measurements.
OUTCOMES
WHAT IMPROVES IN YOUR SYSTEM?Entry-level motor-control parts catch faults between faults: watchdogs, brown-out reset and periodic self-test all run in the gaps. DG32 moves the control loop and the fault check into hardware, so both have a cost you can state in cycles.
ADC sampling, Clarke/Park transforms and PWM generation run in dedicated blocks rather than firmware, so a field-oriented-control tick costs the same number of cycles every time. The CPU is left free for diagnostics.
A trailing checker core compares every value the first core commits, as it commits it. A mismatch trips the FAULT pin and disables the PWM bridge in 39 cycles, on a path that never passes through software.
DG32 targets mature 130 nm/180 nm process nodes qualified at more than one foundry, on a 198-day RTL-to-GDSII shuttle loop. Node maturity and second sourcing are the two things a production schedule actually depends on.
ARCHITECTURE
HOW DO THOSE OUTCOMES RELATE TO THE HARDWARE?The control path runs ADC, CORDIC, PI regulators and PWM, and the CPU only supervises it. The fault-response path runs lockstep comparator, fault latch and PWM brake, and firmware is not in it at all. Sharing nothing but the die is what keeps a busy control loop from delaying a fault response.
Firmware can still prove the fault path works: a locked injection register fires it on purpose, which is the only way to test it on real silicon.
A transient or permanent error changes a value the MAIN core is about to commit.
CHECKER runs the same instructions two cycles later on mirrored inputs and bus responses, so it commits the correct value.
Every committed store is compared. The first mismatch is caught on that store, not at the next software self-test.
A sticky fault latch holds the first cause, because later faults are usually its consequences. Firmware can read it after the fact.
FAULT_N goes low within 39 cycles of an injected fault in simulation. Wired to the gate-driver enable, it stops the bridge without waiting for firmware.
APPLICATIONS
WHERE DOES IT GO?DG32-LITE is one of ten DeepGrid chips, each built to take a socket an imported part holds today. It targets the safety-microcontroller socket in battery packs, motor drives, braking and steering controllers, robot joints and drones, and it is the only one on first silicon. It can also watch the motor it controls for faults, in the cycles left after control.
EVIDENCE
WHAT CAN BE VERIFIED TODAY?DG32 is pre-silicon as of September 2026. Every number on this site carries the kind of evidence behind it. These are five different kinds of evidence, not five stages of a ladder, and none of them is a measurement on fabricated silicon.
| Evidence kind | What it means |
|---|---|
| Simulated | Measured in simulation of the design as built |
| Post-route | Static timing on the placed-and-routed hardened design |
| Analytic | Derived from the architecture, not yet run on a bench |
| Tool estimate | A vectorless power estimate from the implementation tools |
| Process nominal | The 130 nm process limits for each supply domain |
NEXT STEP
WHAT SHOULD YOU DO NOW?Describe the drive, the requirement that decides the design, and the timing you are working to. Ask DeepGrid answers specification questions directly from the whitepaper and technical annex, with the source cited on every answer.