DeepGrid Semi Pvt Ltd designs motor control, condition monitoring and zonal compute on mature nodes. The bet is not that we can beat a 40 nm part on performance. It is that a ≥130 nm part designed in India can be bought where an imported one cannot.
THE MARKET
India imports roughly $23.4B of integrated circuits a year. The mature-node share is the part a 130 nm design centre can actually address, and it is the part where per-seat EDA licensing and mask costs, not transistor density, decide whether a 10,000-unit defence order is profitable.
| Line | Where it lands |
|---|---|
| NRE per chip | ₹0.6–1.2 Cr, against $2–5M for a conventional flow |
| Gross margin at 10k units | 60–75% on defence volumes |
| EDA licensing | ₹0: Yosys, OpenROAD and TritonCTS |
| CPU royalties | ₹0: DGridRiscV is RISC-V, so there is no ARM licence |
| Shuttle cost | ₹14.3L for 100 parts, against $500K–$1M for dedicated masks |
STRATEGY
Sovereignty decides who may buy. Determinism decides what the part is good at. Lockstep decides whether it can be used where a failure destroys hardware.
Three foundries in sequence, not in parallel: SkyWater in the USA for first silicon, IHP in Germany for SiGe radar front-ends, then SCL Mohali in India for sovereign defence production.
WHYThe RTL moves between them without a rewrite, so each migration is a library swap rather than a redesign. SCL Mohali is what earns DAP-2020 Buy (Indian-IDDM); SkyWater and IHP are what make it possible to get there without waiting on domestic capacity first.
One current-control loop costs about 300 hardware cycles, and costs the same at every loop rate. CORDIC runs a Clarke/Park transform in 53–58 cycles.
WHYFirmware that has to meet a deadline is firmware you have to re-time on every change. Moving sampling, the transforms and PWM edges into hardware makes the loop cost a constant, so the CPU keeps only the PI regulators and the remaining headroom is available for diagnostics.
Two RV32IM cores run identical inputs two cycles apart. Every committed store is compared, the first mismatch latches its cause, and FAULT_N drives the gate-driver enable directly.
WHYMotor control drives power electronics, where a silent CPU fault destroys a bridge. Putting the comparator and the trip in hardware takes firmware out of the path entirely. In simulation, an injected fault reaches the bridge in 39 cycles.
MILESTONES
Each step has a job. First silicon proves the architecture; the second spin closes the two largest gaps against the incumbent; connectivity and debug follow.
On SkyWater’s CI2609 shuttle: tapeout 16 September 2026, packaged parts 3 March 2027.
WHAT IT DELIVERSBring-up measures what simulation and static timing predicted: loop cost, fault latency, fmax and power.
A 12-bit multi-channel ADC and embedded flash.
WHAT IT DELIVERSCloses the two largest gaps against the incumbent entry-level motor-control MCU.
CAN-FD, and interactive CPU debug over JTAG.
WHAT IT DELIVERSThe vehicle bus a traction or steering drive expects, and the debug path a production team needs.
The two-clock-domain variant with the INT8 attention engine: design complete, in physical trials.
WHAT IT DELIVERSBring-up will measure the engine’s cycles per query row against the analytic 3,242.
TEAM
What the team is built on, and how large the seed round makes it.
A test die on TinyTapeout-6, on SkyWater sky130, before DG32-LITE taped in.
WHYFirst silicon is not also the first time the tools have produced a die. On a shuttle with no respin, that removes one whole category of surprise.
RTL through to GDSII on Yosys, OpenLane and OpenROAD, with analog and mixed-signal blocks alongside.
WHYNo per-seat EDA licence sits in the cost of a spin. That is what lets a 198-day loop pay for itself at defence volumes, and what lets the RTL move to SCL Mohali by swapping libraries rather than rewriting it.
Five to seven engineers over the 24 months the seed round covers, at a Hyderabad cost base.
WHYThe payroll line is sized to the roadmap on this page, not to a headcount target. It is 24% of the raise.
RECOGNITION
Recognised at the Hyderabad Entrepreneurship Summit for building an edge-first semiconductor and AI ecosystem in India. Source: DeepGrid Semi's own announcement on deepgridsemi.com.
INVESTORS
Every figure here is a target, not a result: nothing is audited and nothing is contracted revenue. The build below is the plan as written. Under it are the two tests the whitepaper runs on its own number, handed to you.
| Year or line | Plan figure |
|---|---|
| Market | India imports ~$23.4B of ICs a year; ~$9B of that is mature node (≥130 nm) |
| FY27 | ₹4 Cr |
| FY28 | ₹28 Cr |
| FY29 | ₹140 Cr |
| FY30 | ₹410 Cr |
| FY31 | ₹1,000 Cr |
Several screened chips; the whitepaper does not split this row
The plan as written. Pull a row, or flood the market.
So the total holds and the split does not — 70 % of FY31 sits on two chips, while chips 9, 7 and 4 are planned at under a tenth of theirs. We would rebalance before an institutional round.
Master whitepaper v3, §13, p. 63
The whitepaper numbers the chips: the two carrying 70 % are chip 2, the smart-meter SoC, and chip 1, the BLDC motor controller; chip 9 is the zonal gateway, chip 7 the 77 GHz radar and chip 4 DG32-LITE.
Rows and crash values are the whitepaper’s own (§12.2, p. 60). Totals are those rows added up; pulling a row and crashing prices together is arithmetic on them, not a forecast.
STRUCTURAL POSITION
Each one is a published instrument with a date or a list attached, rather than an advantage that has to be argued.
Defence tenders that require an Indian designer and manufacturer.
WHYAn importer cannot bid at all, so the competition is domestic or absent.
346+ line items carrying hard import-ban deadlines.
WHYDemand with a date on it, rather than demand that has to be created.
37,696 items listed on the SRIJAN indigenisation portal.
WHYA published list of parts the defence services have already said they want made in India.
SkyWater, then IHP, then SCL Mohali.
WHYEach qualification makes the next SKU cheaper, and no single government can stop the roadmap.
Silicon-validated blocks reused across the SKU roadmap.
WHYThe second chip on a node costs a fraction of the first, which is the whole economic argument for mature nodes.
RISK MANAGEMENT
Each names the trigger and the action, so the decision is not re-argued under pressure.
| Rule | Trigger and action |
|---|---|
| S1: signature gate | If the anchor customer for Chip 2, the smart-meter SoC, has not signed a binding letter by the factory-order cutoff, Chip 2 pauses for one cycle and its capital moves to Chips 1 and 3, the BLDC motor controller and the high-reliability power IC. |
| S2: screening failure | If Chip 6, the voltage supervisor, fails military screening twice, every forward defence revenue projection is deferred by 12 months, across all materials, within 30 days. |
| S3: commercial exit | In FY29, if delivered Chinese component pricing falls below DeepGrid’s bare manufacturing cost, exit ceiling-fan drivers and concentrate on two-wheelers and proprietary modules. |
| S4: SCL Mohali lateness | If SCL Mohali slips by more than two manufacturing cycles, declare the delay publicly and run production only at SkyWater and IHP. |
USE OF FUNDS
Factory runs, mask sets and engineering staff are the two largest lines, in that order.
| Line | Amount | What it buys |
|---|---|---|
| Factory runs and mask sets | ₹3.60 Cr (36%) | Six sky130 MPW runs and one IHP SiGe run (₹1.34 Cr), then two production mask sets and first wafers for Chips 1 and 2, the BLDC motor controller and the smart-meter SoC (₹2.26 Cr) |
| Engineering payroll | ₹2.40 Cr (24%) | Five to seven engineers over 24 months at a Hyderabad cost base |
| Qualification and approval | ₹1.80 Cr (18%) | Four product qualifications: MIL-STD-883, JSS, CEMILAC, and the Chip 6 (voltage supervisor) pathfinder |
| ATE testing line | ₹1.20 Cr (12%) | Automated test equipment, custom load boards, and wafer sort |
| Sales and working capital | ₹1.00 Cr (10%) | Evaluation kits, datasheets, distributor onboarding, and customer engineering |
WHAT THIS PAGE DOES NOT CLAIM
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Tell us the motor, the control requirement and the sensing constraint, and we will route you to the right variant, reference design and engineer.
Pre-silicon. Figures are design values verified in simulation and static timing, not measurements on fabricated parts, unless marked otherwise. Evidence for every figure on this site, and the claims withdrawn after verification, are on the Evidence page.