Measured against the STM32G0, the incumbent entry-level motor-control MCU. DG32 wins on safety hardware and control acceleration; the G0 wins on analog, memory and maturity.
| Dimension | DG32-LITE | STM32G0 series | What it means |
|---|---|---|---|
| CPU | 2 × RV32IM in hardware lockstep, 50 MHz | 1 × Arm Cortex-M0+, up to 64 MHz | Comparable single-thread class. DG32 spends its second core on error detection. |
| Safety hardware | Lockstep comparator, fault latch and FAULT pin, windowed watchdog, supply monitoring, bus-error responses | Independent and window watchdogs, brown-out reset, clock security system; software self-test libraries | Hardware lockstep is otherwise found in automotive MCUs such as Infineon AURIX, NXP S32K and TI Hercules. |
| Program memory | 64 KB mask ROM + external QSPI flash; application runs from SRAM | 16–512 KB embedded flash | G0 executes in place. Embedded flash is on the DG32 roadmap. |
| RAM | 32 KB dual-port SRAM | 8–144 KB SRAM | Enough for control loops; G0B1 has more for communication stacks. |
| Motor PWM | 3-phase with dead-time, centre-aligned ADC trigger, hardware brake; 4 × DShot in hardware | TIM1 advanced timer with dead-time and break; DShot in software | Equivalent 3-phase capability. DShot is native on DG32. |
| Position sensing | Quadrature encoder with index and 3 Hall inputs, decoded in hardware with edge timestamps | Timer encoder mode and Hall sensor interface | Equivalent. |
| Analog | 8-bit differential SAR, ~200 kSa/s, 2 pins | 12-bit, 2.5 MSa/s, up to 16 channels | G0 leads clearly. A 12-bit multi-channel ADC is the first roadmap item. |
| Math | Hardware CORDIC | None (CORDIC appears on STM32G4) | FOC transforms run in hardware on DG32. |
| On-chip AI | DG32-2DOM: INT8 attention engine | None; NanoEdge AI runs in software | Condition monitoring inside the drive itself. |
| Communications | 2 × UART, SPI, I²C, QSPI, 3 × GPIO | Up to 6 × USART, 3 × SPI, 3 × I²C, USB FS, 2 × FDCAN | G0 has the broader catalogue. CAN-FD is on the DG32 roadmap. |
| Test & debug | JTAG test access and scan chains; UART boot monitor | SWD debug; boundary scan on larger packages | Production test is covered. Interactive CPU debug over JTAG is a roadmap item. |
| Process & status | 130 nm; first silicon September 2026 | 90 nm; in volume production since 2018 | DG32-LITE proves the architecture; it is not yet a production part. |
STM32G0 column: public datasheet values for the STM32G0x1 / G0B1 family (Arm Cortex-M0+). DG32-LITE column: first-silicon design values, verified in simulation and static timing, not yet measured on silicon.
WHERE DG32 LEADS
WHERE THE G0 LEADS TODAY
WHY THE DIFFERENCE
Against the G0, DG32-LITE is a comparable single-thread part that spends its second core on error detection.
WHYHardware lockstep is otherwise found in automotive microcontrollers such as Infineon AURIX, NXP S32K and TI Hercules. DG32 brings the mechanism to the entry-level motor-control tier.
An 8-bit, two-input converter against the G0’s 12-bit, 2.5 MSa/s, many-channel ADC.
WHYFirst silicon carries a small converter to prove the analog integration path. The G0 is clearly ahead here, which is why a 12-bit multi-channel ADC is the first roadmap item.
The G0 executes in place from embedded flash; DG32-LITE copies its application from external flash into SRAM.
WHYA flash-less die keeps the 130 nm process simple for a first spin. Embedded flash comes with the second spin.
Analog and program memory first, then CAN-FD and interactive CPU debug.
WHYThe analog front end and program memory are where the incumbent leads most clearly, so they close first. Connectivity and debug follow, while DG32-2DOM proceeds in parallel.
THE MULTI-SPIN ROADMAP
Each step has a job: first silicon proves the architecture, the second spin closes the largest gaps, and connectivity follows.
On the September 2026 multi-project shuttle.
WHAT IT DELIVERSBring-up measures what simulation and static timing predicted: loop costs, fault latency, fmax and power.
12-bit multi-channel ADC and embedded flash.
WHAT IT DELIVERSCloses the two largest gaps against the incumbent.
CAN-FD and interactive CPU debug over JTAG.
WHAT IT DELIVERSThe vehicle bus a traction or steering drive expects, and the debug path a production team needs.
The two-clock-domain variant with the INT8 attention engine.
WHAT IT DELIVERSDesign complete and in physical trials; bring-up will measure the engine’s cycles per query row.
WHAT THIS SITE DOES NOT CLAIM
WHAT TO DO NOW
A drive where hardware lockstep, native DShot or hardware CORDIC decides the part, and an 8-bit converter and boot-from-QSPI are acceptable.
WHYThose are the rows DG32-LITE leads on, and the pinout, package and supplies are fixed enough to lay out a board today.
A drive that needs a 12-bit multi-channel ADC, execute-in-place flash, USB or CAN-FD.
WHYThose are the G0 rows, and the roadmap closes the ADC and flash first, then CAN-FD and interactive debug.