Each field-oriented-control tick samples current, transforms it, regulates it and updates the bridge. DG32 moves every expensive step into hardware, so the loop cost is fixed and known.
On-die SAR ADC, fired by the PWM at the ripple null
CORDIC sin/cos and rotation
Two regulators in plain C on the CPU
CORDIC rotation
Shadow registers load at the next period boundary
Lockstep comparator, continuously
Scrub by scrolling or dragging across the canvas. At 50 MHz, 2500 clock cycles equal exactly one 50 µs loop tick.
Cycle costs measured in simulation at the 50 MHz clock, where one cycle is 20 ns.
WHY THE LOOP RUNS IN HARDWARE
The core fetches every instruction over the bus. That one measured constant is what the whole peripheral set is designed around.
Every instruction is fetched over the bus; there is no instruction cache.
Measured in plain C on this core, against a core with an instruction cache.
Why the converter moved on-die: it was the largest single cost.
The full sensor-to-PWM loop in simulation: about a 100 kHz closed loop.
Centre-aligned PWM makes the switching edges symmetric, so the middle of each period sits at the current-ripple null.
WHYSampling there reads true phase current without the delay of an analog filter. That is why the sample trigger comes from the PWM block, not a timer.
A ~25 kHz carrier was measured as 100 sample triggers in 4 ms, and the ADC clock is sized for loops up to ~100 kHz.
WHYThe carrier and the converter both have headroom; the budget below, not the peripherals, sets the practical loop rate.
An instruction cache or fetch buffer.
WHYThe fetch-bound core is the one constant the peripheral set is designed around. If firmware ever needs more maths than two regulators and an observer, that is where the cycles come from.
The lockstep comparator checks every committed store continuously, at no cost to the loop budget.
WHYSoftware self-test runs periodically and cannot see a fault between runs; the comparator sees it on the store it happens.
LOOP TIMING & BUDGET
One ADC sample, two CORDIC operations and a PWM write cost about 300 cycles at any loop rate. Pick a rate to see what is left for the regulators and observers.
WHAT FITS AT 20 KHZFOC with field-weakening and a state observer
*Derived: CPU budget ÷ ~8 cycles per instruction, the measured cost of this fetch-bound core.
PERIPHERAL LIMITS & CAPABILITIES
Capability and timing per block, from the datasheet’s block notes. Design and simulated values, pending silicon.
| Block | Limit | Note |
|---|---|---|
| UART × 2 | 115,200 baud, 8N1 | Writes wait while busy; a byte is never dropped |
| SPI master | Up to 25 MHz | 0.64 µs per 16-bit word |
| I²C master | 100 / 400 kHz, 7-bit | Clock stretching; a 2-byte read takes ~72 µs at 400 kHz |
| 3-phase PWM | Dead-time up to 5.1 µs | Hardware brake forces all six outputs off in ≤ 2 cycles |
| DShot × 4 | 16-bit frames with CRC | All four channels share one bit-time counter |
| Encoder + Hall | 4× quadrature, index, 3 Hall | Edge timestamps for low-speed velocity |
| SAR ADC | 8-bit differential, ~200 kSa/s | Fired by the PWM sample trigger |
| CORDIC | 20 iterations | 53–58 cycles per operation, fixed |
| DMA | Block moves | ~7.1 cycles per word |
WHAT THE FIGURES ON THIS PAGE REST ON
| Figure | Evidence | Source |
|---|---|---|
| ~100 kHz | Simulated | DG32-LITE Architecture Guide |
| ~300 cycles | Simulated | DG32-LITE Architecture Guide |
| 177 cycles | Simulated | DG32-LITE Architecture Guide |
| 53 to 58 cycles | Simulated | DG32-LITE Architecture Guide |
| ~8 cycles per instruction | Simulated | DG32-LITE Architecture Guide |
| 55 to 62 MHz | Post-route | DeepGrid Datasheets Engineering Specification |
| 82% | Analytic | DG32 AI Architecture |