deepgridSEMI

Pre-Series A · Hyderabad, India

Rendering of the DeepGrid SoC2 package with six compute domains

One silicon.
Infinite possibilities.

DeepGrid designs the chip under its own autonomous systems. One 28 nm die carries fifteen products across trucks, fleets, defence and sensing, built in Hyderabad for a market India has written into law.

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Architectural rendering

products on one die
15
target TSMC process
28 nm
planned die area
57 mm²
sensor fusion target
8.6 ms
TOPS design target
39.3
Concept render of the DeepGrid SoC2 die showing six compute domains
SoC2 die concept: six domains, one tapeout

Four places the chip goes to work.

The same die drives a truck on the highway, a hauler in a port, a forklift in an aisle and a tower on a border. Each scene below is a product line you can open.

Concept renders, not photographs of shipped hardware.

The demand is written into law.

In November 2025 India made five driver-assistance systems compulsory on every truck and bus. Each date below is a deadline with a rule number behind it. None of them is a forecast.

SystemStandardNew modelsEvery model
Emergency braking and stabilityAEBS + VSFAIS-1621 Jan 20271 Oct 2027
Lane departure warningLDWSAIS-1881 Oct 20271 Jan 2028
Driver drowsiness and attention warningDDAWSAIS-1841 Oct 20271 Jan 2028
Blind spot informationBSISAIS-1861 Oct 20271 Jan 2028
Moving-off informationMOISAIS-1871 Oct 20271 Jan 2028

Source: G.S.R. 834(E), 11 November 2025, as amended by G.S.R. 862(E). Management sizes the pool at about one million units a year: 500,000 new vehicles and 500,000 retrofits.

Drag to rotate. Conceptual layout, not a mask.

One die. Six businesses.

Each compute domain on SoC2 is a product line in its own right. Firmware decides which ones a product switches on, so one tapeout serves every buyer.

Sensor-fusion ADAS processor, targeting six cameras, two radars and one LiDAR; 35.96 ms per frame measured on the FPGA prototype, with a SkyWater 130 nm proof-of-concept tape-out on the path to first silicon in 2026. The core compute in every AD kit.

Two clocks.

The FPGA product fills the gap. It ships from Q3 2026, earns while the ASIC is qualified, and runs the same software.

The law

  1. Rules notified in the Gazette
  2. Emergency braking on new truck and bus models
  3. Braking on every model. Warnings on new models
  4. All four warning systems on every model

The silicon

  1. FPGA validated at 40 fps. First defence revenue
  2. FPGA kit ships. 100-unit fleet pilot
  3. First 28 nm silicon from TSMC
  4. Qualified silicon
FPGA module carries the mandate

Law: G.S.R. 834(E) and 862(E). Silicon: Information Memorandum, June 2026, sections 8 and 12. Silicon dates are management plans.

It already runs.

The perception stack is working on hardware today, the patents are filed and the shuttle is contracted. What the round buys is the step from a working FPGA to production silicon.

  • 40fps

    YOLOv11n on an Artix-7 FPGA, 24.8 ms latency

    Measured on hardware, not simulated

  • 15patents

    Provisional filings, March 2026

    Batch-dispatch firmware, 12-bit radar, health processor

  • 130nm

    Earlier tapeout completed at SkyWater

    Six RTL designs now tapeout-ready for 28 nm

  • 96.7%

    Predicted yield on the contracted 28 nm shuttle

    Muse / GSME multi-project wafer, 79-day fab cycle

Source: Information Memorandum, June 2026, section 8. Management figures, not independently verified.

Visual records below show software simulations and a separate DG32 design. They do not verify the hardware performance figures above.

₹45 Cr to take the chip from FPGA to silicon.

Equity at a ₹204 Cr pre-money valuation for 18.07%, plus a ₹10 Cr collateral-free CGTMSE facility for working capital. The tapeout money is released in four gates, and each gate is a point where the next payment can be withheld.