deepgridSEMI

Pre-Series A · Hyderabad, India

The silicon behind every product

One 28 nm chip, SoC2, carries the whole portfolio. Seven short chapters on what it is, why it is built this way, and what still has to be proven. The chip is not yet fabricated: its figures are design targets and derivations.

Drag to rotate. Conceptual layout, not a mask. 39.3 TOPS is a design target.

Pick a product. See where it runs.

Fifteen products, one 28 nm die. Firmware decides which domains a product switches on.

Road Autonomy

Silicon & Compute

Fleet & Mobility

Sensors & Robotics

Smart Truck (AD2 kit)

Runs on one of the six domains:

  • A100 ADAS SoC

The Smart Truck (AD2 kit) The A100 domain

  1. The siliconOne 28 nm die, configured in firmware, becomes fifteen products.DeepGrid Semi's SoC2 is a single monolithic die on TSMC 28 nm HPC+ that fuses eleven sensor channels in 8.6 ms of a 33.3 ms frame budget, leaving 74% of that budget unused. That headroom means every SKU in the portfolio, from a one-camera mirror unit to a full ADAS kit, is a firmware and front-end change, not a new chip programme.~57.1 mm² Die area39.3 TOPS INT8 Peak compute (design target)Read the chapter
  2. Six domainsSix domains on one die means six addressable markets from one tapeout.DeepGrid Semi's ~57.1 mm² die is partitioned into six compute domains, each targeting a distinct industry vertical and carrying its own revenue model. Because all six share a single tapeout, the company enters each market without the NRE burden of a dedicated chip programme.A100 · ~7 mm² ADAS SoCR100 · ~6 mm² Radar SoCRead the chapter
  3. Sensor to computeEleven sensor streams fuse in 8.6 ms, leaving 74% of the frame budget spare.DeepGrid Semi's in-cab compute part accepts seven RGB cameras, two thermal cameras and two radars, eleven configured inputs, and outputs a single fused AD2 perception stream. The reusable product is the compute and software platform; the sensor installation is one application of it, which matters commercially because the same semiconductor can serve multiple truck configurations.11 inputs configured sensor channels7 RGB cameras colour camera countRead the chapter
  4. Measured, not claimedKey performance figures need staged hardware proof before investors should rely on them.DeepGrid Semi's 8.6 ms processing claim and TOPS arithmetic peaks are management figures derived from architecture illustrations, not measurements from fabricated silicon. Investor confidence should be released in stages, FPGA demonstration, ASIC verification, and vehicle qualification, each answering different questions and each requiring reproducible hardware evidence.8.6 ms claimed processing slice33.3 ms frame budget (~30 fps)Read the chapter
  5. Compute waits on dataPer-core data engines proposed to end the queue that stalls arithmetic unitsIn the current shared-dispatch architecture, eight processing cores queue behind a single data-movement engine, leaving compute idle while data waits its turn. Replacing that bottleneck with an independent local DMA per core is the proposed fix, though results remain estimates awaiting testbench evidence.8 cores, 1 engine Shared-dispatch problem470 ms → 85 ms Estimate, not resultRead the chapter
  6. The eight-layer cubeEight hardware layers multiply arithmetic positions eightfold, but the data path decides real throughputThe 8×8×8 compute cube stacks eight 8×8 matrix layers to express reduction depth in hardware rather than software iteration, raising multiply-accumulate positions per cube from 64 to 512 in a single cycle. Two sources project different system-level arithmetic peaks depending on cube count, and both figures are design targets that require workload and implementation validation before they can be treated as measured results.512 MACs / cycle per cube, arithmetic peak34.4 TOPS (design target) portfolio deck, 56 cubesRead the chapter
  7. The far horizonSoC4-A is optionality this raise does not fund, not a commitment.SoC4-A is a far-horizon chip, 1,024 tiles on a 4 nm process, assembled from published open PULP silicon IP, targeting a Q3 2029 tape-out and packaged into a four-chip, 4U rack-mount box called MicroDC-A1. It sits deliberately outside the current plan: SoC2 is the funded business; SoC4-A is the option that business buys investors.16.76 PFLOPS FP4 Peak per chassis~12 PFLOPS FP4 Sustained (projected)Read the chapter

SoC2 is the business.

Every product on this site runs on one 28 nm die. What the round buys is the step from a working FPGA to production silicon; SoC4-A is the option that business buys.