
Aravind Prasad G
Founder & Chief Executive Officer
B.Tech ECE, Bangalore University · Research Associate, IISc Bangalore (speech signal processing) · Stanford SDRM, 2007
Pre-Series A · Hyderabad, India
About
The founders, board, engineering organisation, advisors and the partners contracted for the silicon.

Founder & Chief Executive Officer
B.Tech ECE, Bangalore University · Research Associate, IISc Bangalore (speech signal processing) · Stanford SDRM, 2007
Chief Technology Officer · Silicon architecture
M.Sc. Physics, IIT Gandhinagar

Part-time Director · CMO
Virtual CFO
Independent Director
28 engineers across four domains.
Strategic advisor
Ex-CEO, MosChip Technologies
Financial advisor · placement agent
Sai Emani · Haradatta Emani
ANRF lead PI · IIT Tirupati
Electrical Engineering
ANRF co-PI · IIT Tirupati
Electrical Engineering
Academic advisor · IIT Hyderabad
Computer Science & Engineering
Academic advisor · IMJIR
Founder Director
Specialist firms engaged across fabrication, physical design, IP and board manufacturing for the 28 nm combo die.
TSMC 28 nm HPC+ shuttle for the six-chiplet combo die; 79-day fab cycle.
RTL-to-GDS partner: floorplanning, place and route, timing, DRC/LVS sign-off.
Authored the feasibility reports DGrid-FS-001/002-2026; architecture confirmed feasible.
High-speed PHY hard macros for the 28 nm die.
Artix-7 200T prototype boards and carrier PCBs for the current AD-series pilots.