Silicon · Chapter 7 of 7
The far horizon
SoC4-A is optionality this raise does not fund, not a commitment.
SoC4-A is a far-horizon chip, 1,024 tiles on a 4 nm process, assembled from published open PULP silicon IP, targeting a Q3 2029 tape-out and packaged into a four-chip, 4U rack-mount box called MicroDC-A1. It sits deliberately outside the current plan: SoC2 is the funded business; SoC4-A is the option that business buys investors.
- 16.76 PFLOPS FP4Peak per chassis
- ~12 PFLOPS FP4Sustained (projected)
- 4,096 tiles total4 chips × 1,024
- Q3 2029Tape-out target
- 1,120 WPower envelope
- 256 GB LPDDR5XDRAM per chassis
SoC4-A sits outside the roadmap just presented, introduced here as a separate horizon. It shows investors what the current business is ultimately building toward.
The design places 1024 tiles in a 32x32 mesh on TSMC's 4nm process, targeting 4 petaflops at FP4. These are design parameters shown through animation, not measured silicon.
An animated diagonal wavefront moves across the full grid, illustrating a store propagating from one edge to the other. Moving data efficiently at this scale is the central engineering challenge the mesh must solve.
Each tile is a 5-port router with a safety wrapper, and its internal blocks come from the open PULP platform. FlooNoC, Spatz, ITA, and IDMA are all published, silicon-proven designs, not original sketches.
SoC4-A does not raise the current round; SoC2 is the product that does. The mesh is the long-term option that a successful SoC2 business makes possible.
Inspect full-size figure ↗Technical detail
The MicroDC-A1 is a conceptual product: one 4U, 19-inch rack-mount chassis housing four SoC4-A chips, each carrying 1,024 tiles on a 4 nm process and drawing 280 W under cold-plate dielectric (3M Novec) cooling. Peak compute is 16.76 PFLOPS FP4 dense (4 chips × 4.19 PFLOPS); sustained throughput is projected at approximately 12 PFLOPS FP4, pending validation in the SoftHier simulator, all numbers are provisional pending first silicon. Memory totals 256 GB LPDDR5X-9600 across the chassis, with an aggregate bandwidth design target of approximately 1.84 TB/s, and network connectivity of 2× 400 GbE plus 2× 100 GbE. The Information Memorandum describes use cases including sovereign-AI inference (the ~12 PFLOPS sustained figure is cited as sufficient for approximately 50 concurrent users on a 70B-parameter LLM, or approximately 200 users on a 13B model), robotaxi fleet compute, and telecom edge inference, all described as conceptual. SoC4-A silicon targets a Q3 2029 tape-out; MicroDC-A1 chassis shipment is indicated as 2030 or later.
Portfolio deck, slide 103: SoC4-AInformation Memorandum v2 (Aug 2026), page 17: Roadmap: SoC4-A, FY30 and later