The investment case
DeepGrid Semi is a fabless semiconductor company building a single 28 nm, six-chiplet automotive SoC that underpins fifteen products across ADAS, defence, and industrial autonomy, all from one tapeout. India's ADAS mandates on commercial vehicles create a legislated demand pool of roughly one million units a year, and no indigenous silicon exists at this stage to serve it at a price the market can pay.
The Demand Floor: India has written specific ADAS functions, drowsiness detection, blind-spot monitoring, lane-departure warning, into law for commercial vehicles, with new models from April 2026 and the existing fleet from October. Roughly one million N2/N3 trucks a year fall in scope, making the buying decision a matter of when, not whether. This legislative trigger converts what would otherwise be a discretionary technology sale into a compliance obligation, giving DeepGrid a demand floor that is not dependent on OEM discretion alone. Management projects the plan captures 1.8% of that pool by FY2032.
The Cost Wedge: Foreign silicon prices India out, an imported ADAS module costs multiples of the kit price this market can pay, and no indigenous alternative exists at this stage. Western incumbents' compute board BOMs exceed $6,000, forcing them to target premium, high-margin logistics networks in developed markets. DeepGrid's kit is described as 3–7× cheaper than any import because it owns the chip inside it, and software-only autonomy platforms are structurally squeezed by having to purchase expensive merchant silicon compute engines, a margin trap DeepGrid avoids through vertical integration.
The Platform Multiplier and the Real Risk: One tapeout, structured as $3.17 M across four gated stages, with six of nine de-risking milestones already marked done, seeds four business lines, with management projecting ₹1,128 Cr in FY2032 revenue per the Investment Memorandum; the investor brief separately states ₹1,388 Cr by FY32, and both are management projections contingent on this raise. The central risk the memorandum itself names is schedule: qualified silicon lands H1 2028, after every mandate date, and OEM design-in runs 18–30 months, meaning the next two years are an FPGA business sold through government and PSU channels. Two products carry 64% of projected revenue, so a single certification delay hits ₹720 Cr of the plan simultaneously.
- Tapeout Cost: ~$3.17 M across four gated stages for one ~57 mm² six-chiplet 28 nm SoC, versus ~$18 M if the six chiplets were fabricated as separate dies, a management engineering estimate.
- Revenue Projection: Management projects ₹1,128 Cr by FY2032 per the Investment Memorandum; the investor brief states ₹1,388 Cr by FY32, both are management projections contingent on this raise.
- Concentration Risk: Two products carry 64% of the ₹1,128 Cr revenue plan, a single certification delay hits ₹720 Cr at once.
- Proof of Execution: A 130 nm tapeout is already done, the perception stack runs at 40 fps on FPGA today, and ₹1.01 Cr is contracted via MCEME, pre-revenue but not pre-product.
