deepgridSEMI

Pre-Series A · Hyderabad, India

Silicon · Chapter 2 of 7

Six domains

Six domains on one die means six addressable markets from one tapeout.

DeepGrid Semi's ~57.1 mm² die is partitioned into six compute domains, each targeting a distinct industry vertical and carrying its own revenue model. Because all six share a single tapeout, the company enters each market without the NRE burden of a dedicated chip programme.

  • A100 · ~7 mm²ADAS SoC
  • R100 · ~6 mm²Radar SoC
  • T100 · ~7 mm²Transformer NPU
  • D100 · ~8 mm²Drone SoC
  • S100 · ~7 mm²SDV controller
  • H100 · ~7 mm²Healthcare SoC

A100 · NPU

ADAS SoC

Sensor-fusion ADAS processor, targeting six cameras, two radars and one LiDAR; 35.96 ms per frame measured on the FPGA prototype, with a SkyWater 130 nm proof-of-concept tape-out on the path to first silicon in 2026. The core compute in every AD kit.

Products that rely on it

Specification table of the 57.1 mm² combo die on TSMC 28 nm HPC+, one row per domain: A100, R100, T100, D100, S100 and H100Inspect full-size figure ↗
57.1 mm² combo die: six chiplets, one tapeoutA specification table for a conceptual 57.1 mm² combo die on TSMC 28 nm HPC+ process, listing six sub-processors (A100, R100, T100, D100, S100, H100) with their approximate die areas, business units, and key technical features. The die has not yet been fabricated.One tapeout produces six independently revenue-generating chiplets across mobility, defence, health, and systems markets, avoiding the cost and schedule risk of six separate programmes. The architecture fuses eleven sensor channels in 8.6 ms of a 33.3 ms frame, leaving headroom that allows firmware and front-end changes to configure the same die across fifteen SKUs without a new design.Table from the Information Memorandum
Technical detail

The A100 houses 64 PCOREs × 512 MACs (32,768 MACs total, a design-target 39.3 TOPS INT8) and supports six-camera MIPI CSI-2, making it the core compute for all autonomous-driving kit tiers. The R100 integrates a 12-bit native ADC for 77 GHz FMCW, 4D radar, and 60 GHz mmWave, with an FFT engine and CFAR detector; the sources state the TI AWR2243 is fully eliminated in RTL. The T100 combines a LiDAR point-cloud DSP, a thermal-camera ISP (LWIR MIPI), and an ONNX runtime, and is the inference engine for the autonomous truck edge product line as well as a licensable IP block carrying a stated 90% margin. The D100 is the largest domain at ~8 mm² and pairs an AES-256 secure enclave with lockstep RISC-V (ASIL-B) and ECC SRAM, targeting humanoid, UGV, and drone SoC applications; the sources note ₹1 Cr in institutional defence revenue received in Q1 2026. The S100 handles vehicle networking via CAN FD ×4, Ethernet TSN (IEEE 802.1Qbv), AUTOSAR Adaptive, OTA updates, and C-V2X/5G-NR, with AIS-140 telematics built in, while the H100 integrates a 24-bit bio-ADC for ECG/EEG/SpO2 inference at a design target of under 1 mW continuous, with driver-fatigue and AEB integration covered by Patent 14.

Portfolio deck, slide 5: The siliconInvestment Memorandum: Six chiplets, one 57 mm² dieInformation Memorandum v2 (Aug 2026), page 15: The six-domain die