Silicon · Chapter 6 of 7
The eight-layer cube
Eight hardware layers multiply arithmetic positions eightfold, but the data path decides real throughput
The 8×8×8 compute cube stacks eight 8×8 matrix layers to express reduction depth in hardware rather than software iteration, raising multiply-accumulate positions per cube from 64 to 512 in a single cycle. Two sources project different system-level arithmetic peaks depending on cube count, and both figures are design targets that require workload and implementation validation before they can be treated as measured results.
- 512 MACs / cycleper cube, arithmetic peak
- 34.4 TOPS (design target)portfolio deck, 56 cubes
- 39.3 TOPS (design target)Information Memorandum, 64 cubes
- 600 MHzclock rate assumed
- 8 shared L2 banksmemory service layer
- 8× arithmetic ratioidealized K=8 comparison
Technical detail
The flat 8×8 array holds 64 multiply-accumulate positions and processes reduction depth across successive iterations; the 8×8×8 cube holds 512 positions and expresses that same depth in hardware, so all eight layers fire in one cycle. The 8× arithmetic ratio is an idealized comparison on the same K=8 tile at the same precision and is not an application speedup. The portfolio deck states a system arithmetic peak of 34.4 TOPS, derived from 56 cubes × 512 MACs × 600 MHz × 2 operations; the Information Memorandum states 39.3 TOPS, derived from 64 cubes × 512 MACs at 600 MHz. Both figures are arithmetic ceilings, not benchmarks, and both sources state that targets and arithmetic peaks require workload and implementation validation. Sustained useful work also depends on tensor layout, address distribution across the eight shared L2 banks, arbitration, and compiler scheduling: the sources illustrate that routing all 56 requests to a single bank stalls the array even while seven banks sit idle, making the data path a co-equal design constraint alongside compute geometry.
Portfolio deck, slide 41: Eight layersPortfolio deck, slide 42: E · The computePortfolio deck, slide 43: A stronger data pathPortfolio deck, slide 44: Follow one tilePortfolio deck, slide 45: A hot bankInformation Memorandum v2 (Aug 2026), page 12: The 8×8×8 systolic cube
The screen shows two computing units side by side, both doing identical arithmetic but arranged differently. The contrast sets up exactly why the chip design matters.
The left side shows the 8x8 matrix unit as it runs today on the FPGA, delivering 64 multiply-accumulates per cycle. Because the k reduction is handled in software, it takes 8 cycles to consume one tile.
The right side shows the 8x8x8 cube targeted for the 28-nanometer design, where k is handled in hardware so all 8 layers fire at once, reaching 512 multiply-accumulates per cycle and retiring one tile per cycle.
An animation runs both units simultaneously and the tile counters pull apart, making the 8x throughput difference visible rather than just stated.
The cube, combined with per-core memory access, cannot fit on the FPGA, and that constraint is what drives the move to a custom 28-nanometer part.
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