Silicon · Chapter 4 of 7
Measured, not claimed
Key performance figures need staged hardware proof before investors should rely on them.
DeepGrid Semi's 8.6 ms processing claim and TOPS arithmetic peaks are management figures derived from architecture illustrations, not measurements from fabricated silicon. Investor confidence should be released in stages, FPGA demonstration, ASIC verification, and vehicle qualification, each answering different questions and each requiring reproducible hardware evidence.
- 8.6 msclaimed processing slice
- 33.3 msframe budget (~30 fps)
- 24.7 msarithmetic remainder
- 34.4 TOPS56-core config peak
- 39.3 TOPS64-core config peak
- 600 MHzarithmetic peak clock
Measured
FPGA demonstration
Exercise the software, interfaces and prototype compute.
- 35.96 ms
- end-to-end latency per frame: SSD-MobileNet, edge detection, Harris corner, optical flow
- 28.12 FPS
- real-time throughput of the same pipeline
Today: a working FPGA
Design targets, to verify
Production ASIC
Verify scaled compute, memory, clock, power and area together.
- 8.6 ms
- claimed processing slice of a 33.3 ms frame
- 34.4 / 39.3 TOPS
- arithmetic peak, 56 and 64 cores at 600 MHz
Ahead
Vehicle integration
Test thermal behaviour, safety path and operational conditions.
Ahead
Capital-release gate
Reproducible measurements on the intended configuration.
The roadmap has 9 steps, and 5 are already complete. That progress reduces execution risk for the remaining work.
The first generation ran 64 multiply-accumulates on an Artix-7 FPGA at 125 MHz, producing 3.3 frames per second on a whole frame, with defense revenue supporting it.
Each subsequent FPGA generation adds exactly one capability and then measures the result, keeping risk contained and progress verifiable at every step.
An animation shows frame rate bars rising with each generation, illustrating how the disciplined one-thing-at-a-time approach compounds into meaningful performance gains.
SoC 2, funded by this raise, is designed for 32,768 multiply-accumulates at 600 MHz, targeting 39.3 TOPS and approximately 41 frames per second on AD2, with tapeout planned in Q4 2026.
SoC 3 was taken off the roadmap on purpose, a deliberate simplification worth noting as a sign of disciplined planning rather than scope creep.
Technical detail
The 8.6 ms figure is a management claim against a 33.3 ms frame budget (approximately 30 frames per second); the 24.7 ms remainder is budget subtraction, not measured system headroom, and the measurement boundary, which acquisition, inference, and fusion stages are included, has not been fixed. Two separate compute configurations appear in the source material: a 56-core configuration with a 34.4 TOPS arithmetic peak and a 64-core configuration with a 39.3 TOPS arithmetic peak, both at 600 MHz; neither figure represents measured application throughput, and the sources state the two configurations should not silently stand in for each other. The chip has not been fabricated in 28 nm and no silicon measurements exist; the sources describe the architecture as illustrative, not independently measured silicon evidence. The development plan distinguishes an existing FPGA platform, which exercises software, interfaces, and prototype compute, from the proposed production ASIC, which must separately verify scaled compute, memory, clock, power, and area together. A production advantage depends on the complete platform, compute, memory scheduling, compiler, and integration, and the sources state that arithmetic peaks alone do not establish it.
Portfolio deck, slide 28: Define the measurementPortfolio deck, slide 29: Prove it in stagesPortfolio deck, slide 30: The ladder, runningPortfolio deck, slide 46: Freeze, then measure