Deepgrid Semi
DG32 · LOCKSTEP RISC-V MOTOR-CONTROL SILICONPRE-SILICON · ENGINEERING EVIDENCE
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Twelve architectures. Five system roles.

DeepGrid’s portfolio by the systems it goes into. Open a chip for what it replaces and its SKU Blueprint page; DG32-LITE, the pre-silicon proof point, opens into its diagnostic story: thirty tasks that fit its one core, and the sensor that limits them.

One chip, five system roles. Motors and drives, vehicles, grid and metering, defence and drones, and nearly every board. Concept animation, not product footage; DeepGrid silicon remains pre-silicon.
12 of 12 chips
ChipWhere it goesReplacesNodeMade atEvidence todayNext step
BLDC motor controllerSKU-1Motors and drivesA DRV83xx-class gate driver plus an external MCU, collapsed onto one die with runtime star or delta selection; in fans and appliances, the imported motor-control MCU on every BLDC board.130 nm BCDSkyWater (USA)FPGA-validated: the motor control datapath runs as circuit code on an Artix-7 at 81.25 MHz.RTL ready; analog gate-drive and sensing circuits designed and simulated. First multi-project wafer run, cycle 1; a cost-down cut for fans and appliances is a second tape-out on the same RTL.
Smart-meter SoCSKU-2Grid and meteringAn ADE9153 or V9203-class metering front end plus a separate meter MCU: one chip instead of two.130 nm CMOSSkyWater (USA)FPGA-validated: the meter measurement chain runs as circuit code on the same Artix-7.RTL ready and FPGA-validated; the six-channel analog front end is designed and simulated. Cycle-1 wafer run, alongside SKU-1.
High-reliability power ICSKU-3Defence, avionics and dronesTI and ADI QML power parts in avionics and vetronics units; imported EN 50155-grade power parts in Indian rolling stock and signalling; imported radiation-tolerant PMICs on Indian satellites and launchers.180 nm BCDSCL Mohali (India)Architecture diagram in the SKU Blueprint; prototyping planned on sky130 20 V devices, production at SCL 180 nm.RTL ready for the digital sequencer and telemetry; analog power circuits designed and simulated. The sky130 prototype tests the control logic and low-voltage rails; the 28 V front end and power stage arrive on SCL 180 nm.
DG32-LITE safety microcontrollerSKU-4Motors and drives · Vehicles · Defence, avionics and dronesFunctional-safety microcontrollers of the Microchip and Renesas class.130 nm CMOSSkyWater (USA)Simulation and implementation records; no measured silicon result published.Bring-up
RS-485 and CAN-FD transceiverSKU-5Vehicles · On nearly every boardCAN and RS-485 interface chips from TI, ADI and Renesas, many of which defence platforms can no longer buy.130 nm HVSkyWater (USA)Architecture diagram and status in the SKU Blueprint.RTL ready for the digital logic; analog line drivers designed and simulated. Prototype on the December 2026 shuttle; layout and silicon proof follow.
Voltage supervisorSKU-6On nearly every boardSupervisor chips from TI and Maxim, which sit on almost every circuit board.180 nm CMOSSCL Mohali (India)FPGA-validated: the supervisor sensing chain runs as circuit code on the same Artix-7.RTL ready for the digital logic; comparators and reference designed and simulated. Prototype on sky130, production on SCL 180 nm.
77 GHz 4D radarSKU-7Vehicles · Defence, avionics and dronesImported 77 GHz radar front ends and the processing chips that go with them.0.13 µm SiGe BiCMOSIHP (Germany)Architecture diagram and status in the SKU Blueprint. The SiGe front end has no FPGA equivalent, so it is proven on silicon or not at all.RTL ready for the CMOS signal-processing chip, validated on FPGA. The SiGe front end can only be proven on silicon, on IHP SG13G2.
Rugged display driverSKU-8Defence, avionics and drones · On nearly every boardImported timing-controller and column-driver chipsets in rugged and industrial displays.130 nm HV CMOSSkyWater (USA)Architecture diagram and status in the SKU Blueprint.RTL ready for the digital logic; high-voltage column amplifiers designed and simulated. Layout and silicon proof follow on the first prototype.
Zonal gatewaySKU-9VehiclesImported zonal controllers and CAN, LIN and FlexRay to Ethernet gateways.130 nm CMOS and BCDSkyWater (USA)Architecture diagram and status in the SKU Blueprint.RTL ready; prototype on the December 2026 shuttle, a 130 nm chip at 100 MHz.
DG32-Max secure microcontrollerSKU-10On nearly every boardMAX32655-class imported secure MCUs, and the separate secure element a board adds to boot only signed firmware: one die replaces the pair.130 nm CMOS (SKY130)SkyWater (USA)RTL feature-complete; every bench and firmware test passes, including secure boot on all three test images. No silicon result yet.RTL feature-complete on 1 October 2026; FPGA proof and place-and-route for the December 2026 OpenFrame shuttle follow.
SOH-aware battery-management controllerSKU-11VehiclesThe MCU beside a TI BQ769xx or ADI ADBMS front end, the separate neural accelerator for state-of-health inference, and the authentication chip: three parts become one.130 nm CMOS (SKY130)SkyWater (USA)Block specification: twenty blocks in six groups, reusing the feature-complete DG32-Max platform RTL.Block specification issued September 2026; no wafer-run slot assigned yet.
D100 drone SoCD100Defence, avionics and dronesQualcomm’s QRB5165, the closest comparable chip, which is imported. Most chips in this class do AI or flight control, not both.28 nm; failsafe island buildable at 130 nmSeparate track · ₹50 Cr roundFPGA-validated: the drone position engine runs as circuit code on the same Artix-7.Track B: funded by a separate round once the eleven mature-node chips earn revenue; its lockstep safety core is shared with SKU-4.

Where each chip goes and what it replaces is from the SKU Blueprint, October 2026. DG32-LITE is the detailed pre-silicon case; the wider parts retain their individual architecture and development scope. Concept renders show where a product is used, not the product.

Motors and drives, in depth

DG32-LITE is a safety microcontroller for motors and batteries, and it can watch the machine it controls.

In DeepGrid’s portfolio it is SKU-4, the safety MCU. It is built to take the socket a Microchip or Renesas functional-safety microcontroller holds today: the independent processor in a battery pack, a motor drive, a braking or steering controller, a robot joint or a drone’s redundant flight path, whose job is to catch a fault and shut the system down.

Because it already sits beside the motor, it can do a second job in its spare cycles: watch that motor for faults before they trip anything. A wearing bearing, a broken rotor bar, a pump running dry, a winding getting hot. That is what the thirty tasks on this page are, and every one fits on its single 50 MHz core with no accelerator and no second chip.

24 of the 30 run faster than 1 kHz. The slowest takes 10.3 ms and the largest needs 20 KB. The limit that actually binds is the sensor on the motor, not the chip, and this page says where.

SKU Blueprint, October 2026, page 19 · DG32-AI use-case playbook, pages 1 and 3

It goes into five places, and each one has its own faults worth watching.

The sockets below are DeepGrid’s own. Beside each are the tasks from this page that fit it. That pairing is ours: the portfolio documents name the sockets and the playbook costs the tasks, but neither matches them up.

SKU Blueprint, October 2026, page 19: “Functional-safety microcontrollers from Microchip and Renesas”

  1. EV battery management and motor-safety supervision

    The independent processor that watches a battery pack or a drive and can shut it down. Lockstep cores and the FAULT_N pin are the supervision; the diagnostics add warning before a trip.

  2. Braking and steering controllers

    Drives where a wrong output is a safety event, so a silent CPU fault has to trip in hardware.

    These need the CAN-FD vehicle bus, which is on the roadmap and not on DG32-LITE.

  3. Robot joints

    One controller per joint, running the motor loop and watching the gearbox and load behind it.

  4. The motor-control processor beside a BLDC driver

    The field-oriented-control processor next to SKU-1, DeepGrid’s BLDC motor controller for fans, appliances, EV two- and three-wheelers, robotics and actuator joints.

  5. Flight-critical redundancy for the D100 drone programme

    A second, independent safety processor beside the flight computer. DG32-LITE drives drone speed controllers directly through its four hardware DShot channels.

The SKU Blueprint puts the lockstep MCU on an ISO 26262 ASIL-D path. That is a direction, not a certification: no functional-safety certification is claimed for DG32.

In a motor drive, control comes first. Diagnostics has to fit around it.

A drive switches its power transistors thousands of times a second, and one wrong switching edge can short the bridge. So anything else the processor does must never delay the control loop, and must never be the thing that decides to shut the motor down.

DG32 keeps those two jobs apart. A lockstepped pair of cores and a hardware fault pin hold the trip limits. The diagnostic models on this page only advise: they raise a score or a class, and the deterministic monitor keeps the final say.

Playbook, page 12 · DG32-LITE architecture film, slide 3

Why control comes first

DG32-LITE architecture film · slide 3 · 1:01–1:32

Control costs a fixed amount of hardware time, so what is left is a known budget.

The expensive steps of motor control run in dedicated hardware, so one loop costs about 300 cycles at any loop rate. The diagnostics live in what remains, and the playbook sizes every task against four numbers.

Scalar throughput
12.5 MMAC/s
RV32IM at 50 MHz, int8
Model budget
16.5 KB
29.5 KB with the runtime moved to mask ROM
Free cycles
82 %
with a 10 kHz field-oriented control loop running
Hardware help
CORDIC
sin, cos, atan2 and magnitude, already in the loop

The film and the playbook count different things. The film’s 4,700 cycles at 10 kHz are what is left after the hardware part of one loop; the playbook’s 82 % is what is left for diagnostics with the whole control loop running. The budget for one inference is 12.5 million multiply-accumulates a second divided by the rate: 12.5 thousand at 1 kHz.

Playbook, page 3 · DG32-LITE architecture film, slides 9 and 10

What one control loop costs

DG32-LITE architecture film · slide 9 · 4:00–4:51

On this core, small classical models beat neural networks, and the signal matters more than the model.

Without a multiply array, comparisons and table lookups are the cheap operations. A 100-tree random forest at depth 8 is about 800 comparisons and no multiplies. That is not a compromise: on the CWRU bearing benchmark a random forest over five features reaches 95.6 %, and a review of 42 papers finds support-vector machines at 95 to 100 % against deep methods at 97 to 100 %, statistically the same.

What moves accuracy is the signal. In a twelve-feature ranking study, features taken at the known fault frequency outscored raw statistics four to five times (225.9 against 51.8). So the cycles go to band selection and envelope demodulation first, and a larger model last.

Playbook, pages 4 to 6

The 17 models the thirty tasks use, of the 19 that fit. Inference cost only; feature extraction is costed separately.
ModelWhat it doesCyclesInferenceTasks
LDAPrimary classifier1280.00 ms5
Random forest, 100×d8Primary classifier3,2000.06 ms4
Logistic regressionPrimary classifier1280.00 ms3
Gradient boosting, 200×d4Primary classifier3,2000.06 ms2
Mahalanobis scoreAnomaly score, single scalar4,0960.08 ms2
Extended Kalman filterObserver: sensorless FOC, thermal2,4000.05 ms2
MLP 32-16-8-4Nonlinear classifier or regressor2,6880.05 ms2
Isolation forestUnlabelled anomaly detection3,2000.06 ms1
One-class SVMAnomaly detection with a decision boundary12,8000.26 ms1
k-NN, 200 prototypesField-adaptable classifier25,6000.51 ms1
Nearest centroidOn-device baselining, no backward pass1,0240.02 ms1
Gaussian mixtureRegime identification2,0480.04 ms1
HMM, 8 stateSequence and state tracking3,0720.06 ms1
MLP autoencoderUnsupervised drift detection22,0160.44 ms1
MLP 128-64-32-8Regression at the dense-network ceiling41,9840.84 ms1
GRU, 16 unitsShort sequence modelling147,4562.95 ms1
1D-CNN 8/16/32Raw-waveform classification512,00010.24 ms1

The thirty tasks, one family at a time.

Choose a family to see what each task catches, the signal it reads, the model that runs and what it costs.

8 Rotating machinery

Bearings are the most common motor failure, and an accelerometer catches them.

Bearings account for 44 % of motor failures and are the weakest fault class for current-only sensing, so this family reads vibration. Features taken at the bearing’s own fault frequencies outrank raw statistics four to five times, so the classifier behind them stays small.

ISO 20816 severity zones · ISO 13373 vibration monitoring

Playbook, page 7 and page 11

  1. Bearing fault classification

    Inner race, outer race, ball and cage defects

    Goes into: BLDC motor control

    Signal
    Accelerometer, ≥5 kHz bandwidth · envelope + FFT-256 + moments
    Runs
    Random forest, 100×d8
    Cost
    0.92 ms890 Hz below 1 kHz20 KB

  2. Gearbox and gear-mesh faults

    Tooth damage, mesh-frequency sideband growth

    Goes into: Robot joints

    Signal
    Accelerometer, order-tracked on encoder · envelope + FFT-512 + moments
    Runs
    Random forest, 100×d8
    Cost
    1.69 ms480 Hz below 1 kHz20 KB

  3. Pump cavitation and dry-run

    Separates cavitation, dry running and normal load

    Goes into: BLDC motor control

    Signal
    Phase current + pressure over SPI · FFT-256 + moments
    Runs
    Gradient boosting, 200×d4
    Cost
    0.82 ms>1 kHz12 KB

  4. Fan and blower imbalance

    Blade damage, 1× and 2× amplitude ratio

    Goes into: BLDC motor control

    Signal
    Accelerometer + tachometer · FFT-256 + moments
    Runs
    LDA
    Cost
    0.76 ms>1 kHz0.7 KB

  5. Compressor valve faults

    Valve leakage and flutter against crank angle

    Goes into: BLDC motor control

    Signal
    Accelerometer + crank reference · envelope + FFT-256
    Runs
    Random forest, 100×d8
    Cost
    0.78 ms>1 kHz20 KB

  6. Belt slip and misalignment

    Dual-encoder differential, or vibration harmonic ratio

    Goes into: BLDC motor control

    Signal
    Dual encoder or accelerometer · FFT-256
    Runs
    Logistic regression
    Cost
    0.62 ms>1 kHz0.7 KB

  7. Shaft misalignment and looseness

    1×, 2×, 3× harmonic pattern

    Signal
    Accelerometer · FFT-256 + moments
    Runs
    Random forest, 100×d8
    Cost
    0.82 ms>1 kHz20 KB

Rotor-bar faults sit 40–60 dB down; DG32-LITE’s 8-bit converter resolves 42 dB.

Rotor-bar and eccentricity faults show up as sidebands 40 to 60 dB below the supply frequency. An 8-bit converter resolves 42 dB, so the whole diagnostic range sits at or under its noise floor. Broken rotor bar, air-gap eccentricity and stator inter-turn detection need a 12 to 16-bit converter, or analog suppression and gain ahead of it. The sidebands are also close together, so they need 30 to 100 seconds of record at steady load.

  • Add one accelerometerThe highest-value addition, because bearings are 44 % of motor failures. It needs at least 5 kHz of usable bandwidth, which many low-cost MEMS parts lack, and a stud mount rather than a magnet or adhesive.
  • Add three-phase current and voltageUnlocks stator inter-turn detection and instantaneous power analysis. It needs a multi-channel converter; the part has one differential channel today.
  • Works today, unchangedSensorless observation, plausibility checking, regime identification, anomaly scoring and duty tracking run on the sensing already present, because they read relative change.

Playbook, page 11 (ISO 13373-1, 13373-2, 20958) · DG32-LITE architecture film, slide 14

Where DG32 trails on analog

DG32-LITE architecture film · slide 14 · 6:13–6:41

DG32-2DOM adds an attention engine, on its own clock, for the models the scalar core runs slowly.

None of the thirty tasks needs it. An attention kernel at 64/32/32 is 0.26 million multiply-accumulates, about 21 ms in software on DG32-LITE: it fits, but slowly. DG32-2DOM keeps the same lockstep controller and adds an INT8 engine on a separate clock, behind bridges, so it can never hold up motor control.

So the line is simple. DG32-LITE covers the thirty tasks on this page. DG32-2DOM is for the next class of model, the kind an entry-level motor MCU can only run in software.

Playbook, page 3 · DG32-2DOM architecture film, slides 1 and 12

What DG32-2DOM adds

DG32-2DOM architecture film · slide 1 · 0:00–0:30

What the engine is for

DG32-2DOM architecture film · slide 12 · 5:17–5:49

Diagnostic capability awaits silicon validation; hardware retains the safety trip.

Every latency, memory figure and rate on this page is calculated: feature-extraction cycles plus model cycles, at 4 cycles per int8 multiply-accumulate, against 82 % of a 50 MHz core. That constant is back-solved from the design documents. No workload has been compiled for or measured on DG32-LITE, which has not completed place-and-route.

Accuracy needs the same care. Forty of forty-one reviewed bearing-benchmark studies used splits open to data leakage; on a leakage-free split one classifier fell from 85.8 % to 69.5 %. Expect 65 to 80 % on bearings the model has never seen. That is why the classifier advises and the lockstep monitor holds the trip.

Playbook, page 12 · DG32-LITE architecture film, slides 6 and 16

How the hardware trips the drive

DG32-LITE architecture film · slide 6 · 2:33–2:59

What is not yet measured

DG32-LITE architecture film · slide 16 · 7:14–7:43

Bring a failure mode and a sample rate. We will tell you whether it fits.

If your machine is not among these thirty, the method is the same: the fault, the sensor that sees it, the rate it needs, and the model that fits the budget.

Ask DeepGrid The use-case playbook, 12 pages The control headroom these run in What each kind of figure rests on

Pre-silicon. Figures are design values verified in simulation and static timing, not measurements on fabricated parts, unless marked otherwise.