D100 · 28 nm; 130 nm failsafe island Drone SoC
D100 is a 28 nm drone SoC with its own ₹50 Cr round, raised after mature-node revenue.
Every figure on this page is a design target unless marked otherwise.
- Navigation
- Hardware VIO, six-DoF EKF at 30 Hz
- Failsafe
- Independent watchdog and safe-state machine, isolated power and clock, direct ESC link
- Flight control
- Lockstep DGridRiscV pair, hard real-time PX4 or ArduPilot, on a DO-254 path
D100 is a 28 nm drone SoC with its own ₹50 Cr round, raised after mature-node revenue.
D100 proposes an Indian flight-control and navigation chip, with a failsafe function that remains separate from higher-level computing.
- Job
- Separate flight safety from higher-level perception compute.
- Replaces
- Qualcomm’s QRB5165, the closest comparable chip, which is imported. Most chips in this class do AI or flight control, not both.
- Status
- Track B: funded by a separate round once the eleven mature-node chips earn revenue; its lockstep safety core is shared with SKU-4.
The business case for D100
The Blueprint places it outside the FY31 portfolio revenue plan and proposes a separate ₹50 Cr round after mature-node revenue.
What it replaces
Qualcomm’s QRB5165, the closest comparable chip, which is imported. Most chips in this class do AI or flight control, not both.
Customer opportunity
Indian drone makers, for defence and commercial airframes.
Policy and demand
No Indian chip combines flight control and visual navigation today, and country-of-origin rules bar components from land-border nations.
The delivery trade-off
Vision and AI need tens of millions of transistors within a drone’s power budget, which only a fine node such as 28 nm delivers. The failsafe island, which brings the drone home if the main computer fails, can be built at 130 nm, linking the two tracks.
What D100 claims, what it is worth, and what gates it.
The following mechanisms explain the proposed customer benefit. Each still needs to be validated in the complete product.
D100 is a 28 nm drone SoC with its own ₹50 Cr round, raised after mature-node revenue.
D100 proposes an Indian flight-control and navigation chip, with a failsafe function that remains separate from higher-level computing.
D100 is funded after the eleven mature-node chips earn revenue.
The Blueprint places it outside the FY31 portfolio revenue plan and proposes a separate ₹50 Cr round after mature-node revenue.
28 nm development cost and drone qualification set the D100 case.
The advanced-process development cost and aviation qualification path remain major delivery gates.
Architecture targets, not datasheet values.
Every figure is a design target stated in the SKU Blueprint, page 43. None is a measurement of manufactured silicon.
- 30 HzSix-DoF pose, in hardware
- 10 TOPSOptional AI, phase 2
- 1080p60Vision input
Detailed architecture and specifications
- Process
- 28 nm for flight control, vision and AI; failsafe island buildable at 130 nm
- Flight control
- Lockstep DGridRiscV pair, hard real-time PX4 or ArduPilot, on a DO-254 path
- Navigation
- Hardware VIO, six-DoF EKF at 30 Hz
- Vision input
- MIPI CSI-2, two lanes, to 1080p60, with ISP
- AI (phase 2)
- Optional 10 TOPS INT8/INT4, 2 MB SRAM; attention and softmax in hardware, about 70% less power than a general AI accelerator
- Failsafe
- Independent watchdog and safe-state machine, isolated power and clock, direct ESC link
- Memory
- LPDDR4 32-bit, eMMC or NAND
- Process
- 28 nm; 130 nm failsafe island
- Maturity
- Architecture scope
- Designed toward
- DO-254 · DGCA type certification path · STANAG 4586 · MIL-STD-810H
- Source
- SKU Blueprint, October 2026, page 43
Standards the architecture is designed toward. No DeepGrid part holds a certification or qualification today.
System architecture, signal flow and engineering references
Marker ①: Sensors and the RC link reach two flight cores
Flight control · hard real-time starts with IMU / MAG / BARO over three SPI links at 8 kHz, plus RC + telemetry over SBUS, CRSF or MAVLink. Both reach DGridRiscV × 2: one core for flight control and one for navigation, running the PX4 or ArduPilot loop in hard real time.
Flight control · hard real-time
Marker ②: Cameras feed a pose engine that needs no GPS
In Visual-inertial odometry, frames enter MIPI CSI-2 on two lanes at up to 1080p60. The ISP rectifies them and corrects lens shading, and Feature extracts FAST corners with BRIEF descriptors, about 2k points per frame. The Pose engine is geometry, not learned perception, so it needs neither GPS nor trained weights.
Visual-inertial odometry
Marker ③: A 30 Hz pose reaches the flight loop over the crossbar
The Pose engine fuses features with the IMU in an EKF with IMU pre-integration and sliding-window bundle adjustment, producing a six-degree-of-freedom pose at 30 Hz. It crosses the 128-bit AXI4 crossbar to the flight cores. In phase 2 the NPU, with attention and softmax in hardware, adds object detection on the same 28 nm chip.
Visual-inertial odometryFlight control · hard real-timeAI · phase 2 · on the 28 nm chip
Marker ④: In normal flight, motor commands leave on ESC OUT
The flight loop combines attitude, pilot input and pose into motor commands. ESC OUT sends them as DShot600 on eight channels to the external ESCs and motors. This normal path depends on the flight cores running correctly, and that is exactly what the failsafe path does not assume.
Flight control · hard real-time
Marker ⑤: The link monitor trips the safe state in hardware
The Failsafe island runs on isolated power and clock and watches from outside the mission stack. Its Link monitor detects RC loss, GPS loss or an IMU fault in hardware, not firmware. A trip drives the Safe-state FSM, which selects return to home or land, and the island keeps running when the flight software is what failed.
Failsafe island · isolated power and clock
Marker F: The independent path takes the ESCs on its own
The Independent path drives the ESCs directly, bypassing the flight cores, the odometry and the AI. Recovery does not wait on the computer it is meant to rescue. This establishes a structure, not a result: the architecture does not establish jamming immunity or certified flight safety.
Failsafe island · isolated power and clock
Numbered markers
- ①Marker ①: The IMU, magnetometer, barometer and RC link reach the flight cores.
- ②Marker ②: The cameras run through the ISP and the feature extractor to the pose engine.
- ③Marker ③: The 30 Hz pose reaches the flight loop over the crossbar.
- ④Marker ④: In normal flight, motor commands leave on ESC OUT.
- ⑤Marker ⑤: The link monitor trips the safe-state machine on RC loss, GPS loss or an IMU fault.
- FMarker F: The independent path takes the ESCs directly, without the flight computer.
Block responsibilities
- Flight control
A lockstep DGridRiscV pair, shared with SKU-4 and on a DO-254 certification path, runs the PX4 or ArduPilot loop. The IMU, magnetometer and barometer arrive over three SPI links; motor commands leave as DShot600 on eight channels.
Guide: Flight control- Visual-inertial odometry
Camera input enters over two-lane MIPI CSI-2 at up to 1080p60, passes the ISP and a FAST and BRIEF feature extractor, and the pose engine fuses it with the IMU into a 30 Hz six-degree-of-freedom pose.
Why The odometry is geometry, not learned perception, so estimating a pose needs neither GPS nor a trained model.
Guide: Visual-inertial odometry- AI, phase 2
An INT8 and INT4 NPU of about 10 TOPS class, with 2 MB of SRAM, runs object detection and segmentation for obstacle avoidance, with attention and softmax in hardware at about 70% less power than a general AI accelerator. It is part of the 28 nm chip.
Why Vision AI needs dense logic that 130 nm cannot supply, so it is a separate die the flight functions never depend on.
Guide: AI accelerator (variant 2)- AXI4 crossbar
A 128-bit crossbar joins the flight cores, the pose engine, the NPU and the platform blocks.
Guide: Architecture Overview- Failsafe island
A link monitor detects RC loss, GPS loss and IMU fault in hardware. It trips a safe-state machine that chooses return to home or land, and an independent path drives the ESCs directly.
Why Recovery has to work when the flight software is what failed, so it runs on isolated power and clock and bypasses the flight cores, the odometry and the AI.
Guide: Failsafe island- Platform
2 GB of LPDDR4, eMMC or NAND for logging, a five-domain PMU, secure boot, Ethernet and USB3 for payload and ground link, CAN-FD, SPI and I²C for gimbal and payload, and JTAG.
Guide: Platform- Prototype and product strip
An Artix-7 FPGA at 81.25 MHz validates the position engine; the product is a 28 nm chip, with the failsafe island buildable at 130 nm. FPGA timing closure is a prototype milestone, not a measurement of silicon.
Guide: Prototype and product
Primary sources
- D100 architecture guideEvery block group, both data flows, prototype versus product, and what the architecture does not establish.Opens in the site
- SKU Blueprint, October 2026D100: what it replaces, who uses it, its status and its architecture diagram.PDF · 46 pages
8 integration and validation references
- A Multi-State Constraint Kalman Filter for vision-aided inertial navigationMourikis and Roumeliotis, ICRA 2007: the EKF over a sliding window of camera poses that visual-inertial pose engines build on.University of Minnesota · PDF
- Machine learning for high-speed corner detectionRosten and Drummond, ECCV 2006: the FAST corner detector.Springer · DOI
- BRIEF: Binary Robust Independent Elementary FeaturesCalonder et al., ECCV 2010: the binary descriptor paired with FAST.Springer · DOI
- PX4 autopilot user guideOne of the two open flight stacks the flight cores run.PX4 · Dronecode
- ArduPilot Copter documentationThe other open flight stack the flight cores run.ArduPilot
- MIPI CSI-2 specification overviewThe camera interface the video arrives on.MIPI Alliance
- DShot and bidirectional DShotThe digital ESC protocol the DShot channels speak.Explainer
- Arm AMBA specifications, including AXIThe bus protocol family the on-chip bus and the engine bridges are modelled on.Arm
Background reading explains the general technique each block uses. None of it describes this part or implies its certification.
Architecture from the SKU Blueprint, page 43. A functional view, not a floorplan.
7 questions D100 has to answer before it can be relied on.
The Blueprint’s design and status notes raise these. Each is a question silicon, test or layout has to answer before D100 can be relied on.
Recovery must work when the flight software has failed.Physics
A separate safe-state machine and link monitor in their own power and clock domain, wired directly to the ESCs.
Navigation without GPS.Physics
A hardware visual-inertial engine running a six-degree-of-freedom Kalman filter at 30 Hz.
Vision and AI need tens of millions of transistors inside a drone’s power budget.Physics
A fine node such as 28 nm for the main chip; the failsafe island needs no density and can be built at 130 nm, linking the two tracks.
Hardware failsafeOpen
Why is the safe-state logic separate hardware rather than a task in the flight stack, and what does it need to see to act?
GPS-denied driftOpen
Can the 30 Hz pose engine hold under 1% drift per kilometre under jamming, without learned weights?
Thermal envelopeOpen
How is heat removed in a closed fuselage at +55 °C with the camera pipeline and flight loops running?
Two nodes, one airframeOpen
If the failsafe island is built at 130 nm beside a 28 nm main chip, how is its independent power, clock and ESC path kept isolated across the package?
An architecture, with its evidence named.
- Strongest evidence
- FPGA-validated: the drone position engine runs as circuit code on the same Artix-7.
- Development status
- Track B: funded by a separate round once the eleven mature-node chips earn revenue; its lockstep safety core is shared with SKU-4.
The failsafe architecture does not establish jamming immunity, certified flight safety or an awarded silicon contract.
How every figure on this site was obtainedThe systems it goes into, and the parts beside it.
Safe-state behavior, compute partition, power isolation and flight validation.
Parts beside it
Read the source behind every figure.
Each document opens inside the site at the cited section; the PDF is the edition of record.
- SKU Blueprint, October 2026 (11 SKUs + D100)D100, page 43 · source of recordPDF · 46 pages
- Mature-Node Silicon for India’s Defence (Whitepaper v3)Evidence for this partPDF · 71 pages
Design files
Bring the socket. We will tell you what D100 has to prove for it.
Send the platform, voltage and power environment, interfaces and qualification needs. The reply names what is architecture, what is evidence and what would have to be tested.