SKU-7 · IHP SiGe + 130 nm CMOS 77 GHz radar
SKU-7 sweeps 4 GHz at 77 GHz for 3.75 cm range resolution and tracks up to 64 targets.
Every figure on this page is a design target unless marked otherwise.
- Sweep
- 4 GHz in the 76 to 81 GHz band; 3.75 cm range resolution
- Array
- Two transmit, four receive (MIMO)
- Processing
- Range and Doppler FFT, CFAR, angle estimation, 64-target tracker
SKU-7 sweeps 4 GHz at 77 GHz for 3.75 cm range resolution and tracks up to 64 targets.
SKU-7 separates radio-frequency sensing from digital processing, targeting radar functions for vehicles and other platforms.
- Job
- Convert radio-frequency reflections into range and motion information.
- Replaces
- Imported 77 GHz radar front ends and the processing chips that go with them.
- Status
- RTL ready for the CMOS signal-processing chip, validated on FPGA. The SiGe front end can only be proven on silicon, on IHP SG13G2.
The business case for SKU-7
Choose the detection task, operating environment and required range before selecting a radar architecture.
What it replaces
Imported 77 GHz radar front ends and the processing chips that go with them.
Customer opportunity
Automotive radar, plus defence radar after approval.
Policy and demand
Defence procurement lists name radar warning receivers for the Su-30 MKI and Mi-17, weapon-locating radar, battlefield surveillance radar, and shipborne and precision-approach radar.
The delivery trade-off
The one part where the process is a hard limit: 130 nm CMOS cannot reach 77 GHz. Fine-node RF-CMOS (40–45 nm) can, at a much higher mask cost, so the front end uses IHP’s silicon-germanium process.
What SKU-7 claims, what it is worth, and what gates it.
The following mechanisms explain the proposed customer benefit. Each still needs to be validated in the complete product.
SKU-7 sweeps 4 GHz at 77 GHz for 3.75 cm range resolution and tracks up to 64 targets.
SKU-7 separates radio-frequency sensing from digital processing, targeting radar functions for vehicles and other platforms.
Two dies: SiGe for 77 GHz RF, 130 nm CMOS for range, Doppler and tracking.
Choose the detection task, operating environment and required range before selecting a radar architecture.
The SiGe front end has no FPGA equivalent; only silicon proves it.
The radio and processing combination must be proven together in the intended scene.
Architecture targets, not datasheet values.
Every figure is a design target stated in the SKU Blueprint, page 28. None is a measurement of manufactured silicon.
- 4 GHzChirp sweep
- 3.75 cmRange resolution
- 64Tracked targets
Detailed architecture and specifications
- RF process
- 130 nm SiGe BiCMOS (IHP SG13G2), fT above 350 GHz
- Baseband process
- 130 nm CMOS signal-processing chip; RTL validated on FPGA
- Bands
- 77 GHz; 24 GHz variant
- Array
- Two transmit, four receive (MIMO)
- Sweep
- 4 GHz in the 76 to 81 GHz band; 3.75 cm range resolution
- Conversion
- Four 12-bit 40 MSPS ADCs
- Processing
- Range and Doppler FFT, CFAR, angle estimation, 64-target tracker
- Interfaces
- CAN-FD, 100BASE-T1, MIPI CSI-2
- Process
- IHP SiGe + 130 nm CMOS
- Maturity
- Architecture scope
- Designed toward
- ISO 26262 ASIL-B · DO-160G · MIL-STD-883K
- Source
- SKU Blueprint, October 2026, page 28
Standards the architecture is designed toward. No DeepGrid part holds a certification or qualification today.
System architecture, signal flow and engineering references
Marker ①: A crystal, a PLL and a 38.5 GHz VCO shape the chirp
The chirp starts in Chirp synthesis + transmit on the SiGe die. A 40 MHz XTAL clocks the Ramp gen, which sets a sawtooth or triangle chirp profile. A fractional-N PLL with a 1 MHz loop bandwidth steers a 38.5 GHz VCO built on SiGe HBTs. The ramp must stay linear across the whole 4 GHz sweep, or the radar sees ghost targets.
Chirp synthesis + transmit · SiGe die
Marker ②: A doubler reaches 77 GHz and two PAs transmit
The × 2 block doubles the VCO to 77 GHz, so the oscillator runs at half the carrier. PA · TX1 and PA · TX2 each transmit at 13 dBm. The same × 2 output feeds the LO to every receive mixer, so transmit and receive share one chirp. A 4 GHz sweep in the 76 to 81 GHz band gives 3.75 cm range resolution.
Chirp synthesis + transmit · SiGe die
Marker ③: Four receive channels mix each echo down to IF
Echoes return to the Receive array, four identical channels on the SiGe die. LNA × 4 amplifies each at a 3.5 dB noise figure, Mixer × 4 mixes it with the LO, IF amp × 4 lifts it, and AAF × 4 filters it at 10 MHz. The beat frequency carries range; the phase across the four receivers carries the angle of arrival.
Receive array · 4 channels · SiGe die
Marker ④: The IF signals cross the die boundary once
This is the only die crossing. The four IF signals leave the SiGe die for ADC × 4 in Signal processing on the CMOS die: four 12-bit converters at 40 MSPS. Windowing applies Hann or Blackman, a 1024-point radix-4 Range FFT takes 26 µs per chirp, and a 128-point Doppler FFT across chirps fills the Range-Doppler map in 512 KB of SRAM.
Receive array · 4 channels · SiGe dieSignal processing · CMOS die
Marker ⑤: CFAR and beamforming turn the map into detections
The Range-Doppler map feeds Detection + output on the CMOS die. Cell-averaging CFAR holds a constant false-alarm rate against the background clutter, and Angle est uses digital beamforming across the four receivers to resolve angle to 15°. Each detection now carries range, velocity and angle.
Signal processing · CMOS dieDetection + output · CMOS die
Marker ⑥: Up to 64 tracked targets leave for the vehicle ECU
The Target list holds range, velocity, angle and RCS for up to 64 tracks per frame. It leaves the package for the ECU over CAN-FD, 100BASE-T1 or MIPI CSI-2. Everything before this point stays inside the two dies, so the host system receives targets rather than raw radar samples.
Detection + output · CMOS die
Numbered markers
- ①Marker ①: The crystal, ramp generator, PLL and VCO synthesise the chirp.
- ②Marker ②: The doubler reaches 77 GHz and the two PAs transmit.
- ③Marker ③: Each of four echoes is amplified, mixed with the LO, filtered.
- ④Marker ④: The IF signals cross the die boundary and four 12-bit converters digitise them for the range FFT.
- ⑤Marker ⑤: The range-Doppler map feeds CFAR detection and angle estimation.
- ⑥Marker ⑥: The target list goes to the ECU over CAN-FD, 100BASE-T1 or MIPI CSI-2.
Block responsibilities
- Chirp synthesis + transmit · SiGe die
A 40 MHz crystal, a ramp generator, a fractional-N PLL, a 38.5 GHz SiGe VCO and a doubler to 77 GHz, feeding two 13 dBm power amplifiers.
Why A 4 GHz sweep gives 3.75 cm range resolution, and only a SiGe HBT reaches 77 GHz on a mature node.
Guide: Chirp synthesis + transmit · SiGe die- Signal processing · CMOS die
Four 12-bit 40 MSPS converters digitise the IF signals as they cross the die boundary; windowing, a 1024-point radix-4 range FFT, a 128-point Doppler FFT and a range-Doppler map in 512 KB of SRAM follow.
Guide: Signal processing · CMOS die- Receive array · 4 channels · SiGe die
Four identical channels: a 3.5 dB noise-figure LNA, a mixer fed by the LO, an IF amplifier and a 10 MHz anti-alias filter; the IF signals leave the SiGe die for the converters.
Why The beat frequency carries range; the phase across the four receivers carries the angle of arrival.
Guide: Receive array · 4 channels · SiGe die- Detection + output · CMOS die
Cell-averaging CFAR detection, digital-beamforming angle estimation at 15° resolution from four receivers, and a target list of up to 64 tracks per frame.
Guide: Detection + output · CMOS die
Primary sources
- SKU-7 architecture guideEvery block group, the data flows and the design targets.Opens in the site
- SKU Blueprint, October 2026SKU-7: what it replaces, who uses it, its status and its architecture diagram.PDF · 46 pages
2 integration and validation references
- The fundamentals of millimeter wave radar sensors (TI SPYY005)FMCW chirps, beat frequency, range and velocity FFTs and angle estimation.Texas Instruments · PDF
- IHP SG13G2 open PDKThe open SiGe BiCMOS process the front end is drawn on.IHP · GitHub
Background reading explains the general technique each block uses. None of it describes this part or implies its certification.
Architecture from the SKU Blueprint, page 28. A functional view, not a floorplan.
7 questions SKU-7 has to answer before it can be relied on.
The Blueprint’s design and status notes raise these. Each is a question silicon, test or layout has to answer before SKU-7 can be relied on.
Gain at 77 GHz.Physics
SiGe heterojunction transistors with transition frequency above 350 GHz; standard CMOS lacks the margin.
Range resolution of 3.75 cm.Physics
A 4 GHz chirp sweep with a linear, low-noise frequency ramp.
Fast converters and FFTs next to sensitive RF.Physics
The converters sit on the CMOS die, across a package boundary from the RF.
The die boundaryOpen
What substrate transmission lines keep the IF signal clean between the SiGe and CMOS dies?
Chirp linearityOpen
Can the ramp hold under 50 kHz rms error across 4 GHz without ghost targets?
Silicon riskOpen
With no FPGA stand-in for the front end, how is risk reduced across IHP wafer runs?
Co-existenceOpen
On a mast beside UHF and VHF radios, what shielding keeps local-oscillator harmonics out of them?
An architecture, with its evidence named.
- Strongest evidence
- Architecture diagram and status in the SKU Blueprint. The SiGe front end has no FPGA equivalent, so it is proven on silicon or not at all.
- Development status
- RTL ready for the CMOS signal-processing chip, validated on FPGA. The SiGe front end can only be proven on silicon, on IHP SG13G2.
RF and baseband are different dies; transistor frequency capability is not the radar operating frequency.
How every figure on this site was obtainedThe systems it goes into, and the parts beside it.
RF channels, waveform, sampling, processing and package partition.
- VehiclesDeepGrid’s own truck mirror-tower radar, and automotive emergency braking.
- Defence, avionics and dronesDefence perimeter and counter-drone radar.
Parts beside it
Read the source behind every figure.
Each document opens inside the site at the cited section; the PDF is the edition of record.
Design files
Bring the socket. We will tell you what SKU-7 has to prove for it.
Send the platform, voltage and power environment, interfaces and qualification needs. The reply names what is architecture, what is evidence and what would have to be tested.