The investment brief.
What tranche 1 buys, how the SKU Blueprint and the September financial model relate, and six buyer questions answered with what is proven and what is a target.
Plan targets and estimates, not results. Written 13 Oct 2026 from the SKU Blueprint (October 2026), the financial model (corrected v3, September 2026) and the DG32 preliminary datasheets. The live figures are on the SKU portfolio page and the business plan.
₹10 Cr targets first silicon for nine chips.
Tranche 1 plans nine of eleven chips for the 26 Dec 2026 shuttle carrying ₹925 Cr of the ₹1,000 Cr plan lines. The Blueprint's FY31 chip ramp is 13.5× the September model's chip line. Review the reconciliation below; these are different plans and revenue scopes.
Revenue, capital and qualification priorities
- 76 %Most of tranche 1 buys silicon
Nine prototypes, respin reserve, engineering team: ₹7.6 Cr of the ₹10 Cr. The rest is approvals, tools and contingency.
SKU Blueprint, Oct 2026 · plan targets - 13.5×The two plans disagree on chips
FY31 chip revenue: ₹608 Cr in the Blueprint against ₹45 Cr in the model, whose ₹594.3 Cr total is mostly Systems.
Blueprint, Oct 2026; model v3, Sep 2026 · plan targets - ₹10.1 CrCash is tightest in FY29
Lowest closing cash in model v3, at the end of FY29, before chip and Systems revenue catch up.
Model v3, Sep 2026 · plan target - ₹41.7–91.2 CrFull development is a later raise
Estimated development cost for all eleven chips (₹31.9–70.6 Cr for the nine on the shuttle). Tranche 1 funds prototypes, not full development.
SKU Blueprint, Oct 2026 · estimates
Tranche 1 funding and first-silicon milestones
Three of the nine carry ₹541 Cr of their ₹601 Cr FY31 ramp: SKU-1, SKU-2, SKU-10.
- Plan line (full rate)
- FY31 ramp
Left: plan targets, SKU Blueprint (Oct 2026). Right: approval months by first market, the Blueprint's approval table; which market each chip enters first is an estimate.
Company and chip revenue plans require reconciliation
The two plans meet in FY31 only by coincidence: ₹608 Cr of chips in the Blueprint, ₹594.3 Cr for the whole company in the model, of which chips are ₹45 Cr.
- Blueprint: chips
- Model: chips (Semiconductors)
- Model: whole company
SKU Blueprint ramp table (Oct 2026); financial model corrected v3 (Sep 2026), revenue by segment. Plan targets. The model's chip line predates the Blueprint; a model v4 with the Blueprint ramp is due before tranche 2.
The Blueprint raises ₹50 Cr of equity in two tranches; the model raises ₹55 Cr, ₹10 Cr of it as a loan. Per-chip margins sit below the model's 84 %.
- Tranche 1, equity
- Tranche 2, equity (May 2027)
- Equity
- CGTMSE-backed loan
Capital: SKU Blueprint equity table and financial model sources of funds. Margins: SKU Blueprint unit-cost table (estimates, no silicon yet); the model's FY31 gross profit ₹501.0 Cr on revenue ₹594.3 Cr.
Investment risks and funding requirements
Investment diligence: funding, readiness and revenue assumptions.
- 1
What exists today: any silicon, any customers?
No silicon and no customers yet
- Shown so far
- Two DG32 dies taped out and hardened; lockstep core closes at 55–62 MHz post-route
- Target or estimate
- SKU-10 at 100 MHz; demand from buyers obliged to buy domestic (a thesis)
Evaluation requirements and assumptions
No silicon and no customers. DG32-LITE and DG32-2DOM are taped-out RTL and hardened die, pre-silicon (preliminary datasheets, 12 Sep 2026). The DG32-LITE lockstep core closes at 55–62 MHz in post-route timing, a pre-silicon result; the datasheet specifies 50 MHz, and SKU-10's 100 MHz is a design target (SKU Blueprint, Oct 2026). The datasheets specify the 8-bit ADC as untrimmed. There are no purchase orders or letters of intent today. The demand case is that Indian buyers in metering, defence and industrial are already obliged to buy domestic; that is a thesis, not a booked order.
- 2
What does ₹10 Cr buy, and how will I know it worked?
Nine prototypes, respins, the team and first approvals
- Shown so far
- Line-by-line uses summing to ₹10.0 Cr
- Target or estimate
- Nine designs on the 26 Dec 2026 shuttle; first silicon on boards; SKU-6 and meter approvals started
Evaluation requirements and assumptions
It buys nine prototypes on the 26 Dec 2026 shuttle (₹2.6 Cr, about ₹0.29 Cr each), a respin reserve for about eight re-runs (₹2.5 Cr), the engineering team (₹1.0 Cr to March 2027, ₹1.5 Cr for the next 12 months), first approvals (₹1.0 Cr: SKU-6 military screening, meter certification with a partner), tools and lab (₹1.0 Cr), contingency (₹0.3 Cr) and boards (₹0.1 Cr). Source: SKU Blueprint (Oct 2026), plan targets. The milestones are: nine designs on the shuttle by 26 Dec 2026; first silicon brought up on boards; approvals started for SKU-6 and the meter SoC. The silicon return date is not stated in any source document, so no date is committed until ChipFoundry confirms it.
- 3
The Blueprint says ₹608 Cr in FY31 and the model says ₹594 Cr. Which is it?
Different scopes: chips alone vs the whole company
- Shown so far
- The model's chip line is ₹45.0 Cr in FY31; Systems is ₹501.9 Cr
- Target or estimate
- A model v4 with the Blueprint ramp as its chip line, before tranche 2
Evaluation requirements and assumptions
Neither contradicts the other; they measure different things. ₹608 Cr is chip revenue alone (SKU Blueprint, Oct 2026). ₹594.3 Cr is total company revenue, of which chips are ₹45.0 Cr and Systems ₹501.9 Cr (financial model v3, Sep 2026). Both are plan targets. The model predates the Blueprint and has not taken in its ramp; a model v4 with the Blueprint ramp as its chip line is due before tranche 2.
- 4
When does chip revenue start, and what slows it?
FY29, ₹70 Cr, then approval times set the pace
- Shown so far
- Approval routes and their time ranges are named per market
- Target or estimate
- 6–12 months industrial, 12–18 meters, 18–36 automotive and defence (estimates)
Evaluation requirements and assumptions
The Blueprint's first chip revenue is ₹70 Cr in FY29 (Apr 2028–Mar 2029), from DG32-Max and the motor controller (plan target). Both sell into industrial markets, where customer qualification takes 6–12 months; smart meters take 12–18 months (BIS IS 16444 plus a utility tender). Automotive and defence take 18–36 months (AEC-Q100 and design-in; MIL screening and vendor listing), which is why the automotive group carries only ₹18 Cr and the defence group ₹28 Cr of the FY31 ramp. Approval times are estimates from the Blueprint's approval table. The FY29 start also depends on first silicon working, which no one has measured yet.
- 5
How much capital does this take, and do the margins hold?
₹41.7–91.2 Cr to develop; ₹50 Cr covers the low case
- Shown so far
- Unit cost estimated for four chips
- Target or estimate
- 53–82 % gross margin per chip; the model assumes 84 % in FY31
Evaluation requirements and assumptions
Development cost for all eleven chips is ₹41.7–91.2 Cr (estimate, SKU Blueprint, Oct 2026). The Blueprint's two tranches total ₹50 Cr, which covers the low case; the high case needs more. The September model raises ₹55 Cr (₹45 Cr equity plus a ₹10 Cr CGTMSE-backed loan) and its closing cash bottoms at ₹10.1 Cr at end FY29 (plan target). On margin, the Blueprint costs four chips at 53–82% gross margin: for example the voltage supervisor at $0.09–0.17 to make against $0.20–0.80 prices, and DG32-Max at $1.30–2.30 against $3–8 (estimates, no silicon yet). The model's FY31 gross margin of 84% is above that range.
Tranche 1 funding, milestones and investment assumptions
Lead with the SKU Blueprint for tranche 1: its ₹10 Cr use-of-funds table is the ask, and its FY31 chip ramp (₹608 Cr) is not the same number as the September model's FY31 revenue (₹594 Cr), even though they look close.
Sources and labels. SKU Blueprint (October 2026, current); financial model, corrected v3 (September 2026); DG32-LITE and DG32-2DOM preliminary datasheets (12 Sep 2026); DeepGrid business overview. Every Blueprint and model figure is a plan target, not a result; nothing here is audited or contracted. Approval times, market sizes, unit costs and margins are estimates.
Nine chips carry ₹925 Cr of the ₹1,000 Cr plan and go on the 26 Dec 2026 shuttle
Nine of eleven Blueprint chips go on the ChipFoundry December 2026 shuttle; tranche 1 pays about ₹0.29 Cr each to get them there (SKU Blueprint, Oct 2026). Together they hold ₹925 Cr of plan lines and ₹601 Cr of the FY31 ramp, all plan targets. Four of the nine sell into markets where approval takes 18–36 months, so the FY31 ramp leans on three: SKU-1, SKU-2 and SKU-10 (₹541 Cr of ₹601 Cr).
| SKU | Chip | Plan line ₹ Cr | FY31 ramp ₹ Cr | First market (approval route) | Approval, months (est.) | Readiness | Dev cost ₹ Cr (est.) |
|---|---|---|---|---|---|---|---|
| SKU-1 | BLDC Motor Controller | 320 | 256 | Industrial (customer qualification) | 6–12 | RTL + analog schematics | 5.2–11.1 |
| SKU-2 | Smart-Meter SoC | 250 | 175 | Smart meters (BIS IS 16444 + utility tender) | 12–18 | RTL + analog schematics | 2.2–4.6 |
| SKU-10 | DG32-Max Secure MCU | 110 | 110 | Industrial (customer qualification) | 6–12 | RTL | 2.1–4.3 |
| SKU-9 | SDV Zonal Gateway | 60 | 6 | Automotive (AEC-Q100 + design-in) | 18–36 | Digital RTL | 3.8–8.8 |
| SKU-5 | Interface Transceiver | 45 | 14 | Meters, industrial | 6–18 | RTL + analog schematics | 3.9–9.3 |
| SKU-3 | Hi-Rel PMIC | 40 | 12 | Defence first (MIL screening + vendor listing) | 18–36 | RTL + analog schematics | 5.0–11.1 |
| SKU-4 | Lockstep MCU (DG32-LITE die) | 40 | 4 | Automotive (AEC-Q100 + design-in) | 18–36 | RTL; die hardened and taped out per datasheet | 3.4–7.8 |
| SKU-6 | Voltage Supervisor | 40 | 16 | Defence first (MIL screening + vendor listing) | 18–36 | RTL + analog schematics | 3.9–8.3 |
| SKU-8 | Display Driver | 20 | 8 | Meters, industrial | 6–18 | RTL + analog schematics | 2.4–5.3 |
| Nine on shuttle | 925 | 601 | 31.9–70.6 |
Plan lines, ramp, readiness and dev cost: SKU Blueprint (Oct 2026), plan targets and estimates. Approval months: the Blueprint's approval table by market; which market each chip enters first is read from the Blueprint's ramp groups and tranche 1 uses (SKU-6 military screening, meter certification), so treat the mapping as an estimate.
- Not on the shuttle: SKU-7 4D Radar RF (digital RTL only; SiGe front end) and SKU-11 BMS Controller (specification; no MPW slot). Together ₹75 Cr of plan lines, ₹8 Cr of FY31 ramp. D100 (28 nm, Track B) has no plan line.
- Clock, SKU-4 and SKU-10: the Blueprint lists 100 MHz, a design target. The DG32-LITE datasheet (12 Sep 2026) specifies 50 MHz; the lockstep core closes at 55–62 MHz in post-route timing, pre-silicon. No silicon has been measured.
- Readiness, SKU-4: the Blueprint says RTL; the DG32-LITE datasheet (12 Sep 2026) says taped-out RTL and hardened die. Both are pre-silicon.
- ₹1 Cr rounding inside the Blueprint: SKU-2, SKU-5 and SKU-8 sum to ₹197 Cr in FY31, but the Blueprint's ramp table shows that group at ₹196 Cr. All eleven SKUs sum to ₹609 Cr against the ₹608 Cr total. Quote ₹608 Cr and say it is the Blueprint's table total.
The two plans agree on FY31 revenue only by coincidence
The Blueprint's ₹608 Cr FY31 ramp is chip revenue alone; the September model's ₹594.3 Cr FY31 is the whole company, and only ₹45.0 Cr of it is chips. The model's FY31 revenue is mostly its Systems segment (₹501.9 Cr), with Robotics ₹28.9 Cr and Sensors ₹18.5 Cr. Neither document has absorbed the other, so an investor who adds them, or swaps one for the other, gets a wrong picture.
| Item | SKU Blueprint (Oct 2026) | Financial model v3 (Sep 2026) | How to read it |
|---|---|---|---|
| Capital | ₹50 Cr equity in tranches: ₹10 Cr, then ₹40 Cr | ₹55 Cr: ₹45 Cr equity + ₹10 Cr CGTMSE-backed loan | Different structures; the model adds debt and ₹5 Cr more |
| What tranche 1 / early capital buys | ₹10 Cr: prototypes ₹2.6 Cr, respin reserve ₹2.5 Cr, team ₹2.5 Cr, approvals ₹1.0 Cr, tools and lab ₹1.0 Cr, contingency ₹0.3 Cr, boards ₹0.1 Cr | Tape-out capex ₹18 Cr (FY27), ₹10 Cr (FY28), ₹2 Cr (FY29); other capex ₹1–5 Cr a year | The Blueprint's table is line-by-line and sums to ₹10.0 Cr; the model has no tranche split |
| Development cost | ₹41.7–91.2 Cr for all eleven chips; ₹31.9–70.6 Cr for the nine on the shuttle (estimates) | ₹30 Cr tape-out capex over FY27–FY29, plus R&D in the P&L | ₹50 Cr of Blueprint tranches covers the low case, not the high case |
| First chip revenue | FY29: ₹70 Cr (DG32-Max and motor controller) | Semiconductors: ₹0.05 Cr FY28, ₹5.2 Cr FY29 | 13.6× apart in FY29 |
| FY31 chip revenue | ₹608 Cr (table total; SKUs sum to ₹609 Cr) | ₹45.0 Cr Semiconductors segment | The core gap: 13.5× |
| FY32 | ₹844 Cr chips | ₹104.0 Cr chips; ₹1,128.5 Cr total | Model total exceeds the chip ramp only because of Systems |
| Process scope | 130 nm SKY130; D100 at 28 nm as Track B with no plan line | R&D line "SoC4 5nm tape-out program": ₹95.1 Cr in FY31, ₹169.3 Cr in FY32 | A 5 nm programme appears only in the model |
| Margin | Gross margin 53–82% on four costed chips (estimates, Oct 2026) | Gross margin 84% in FY31 (₹501.0 Cr on ₹594.3 Cr) | Model margin sits above the Blueprint's per-chip range |
| Cash low point | Not modelled | Closing cash ₹10.1 Cr at end FY29 (Mar 2029), lowest year | Tranche timing in the Blueprint has no cash curve behind it |
SKU Blueprint (Oct 2026) ramp table; financial model corrected v3 (Sep 2026) revenue by segment and P&L. Plan targets.
Recommendation. Present the Blueprint as the chip plan and the ₹10 Cr table as the ask. Describe the September model as the company-wide plan written before the Blueprint, and say plainly that its chip line (₹45 Cr in FY31) predates the Blueprint ramp. Commit to a model v4 that takes the Blueprint ramp as its Semiconductors line before tranche 2.
Five questions: answer each with what is proven, then what is a target
The honest line through all five: no silicon and no customers yet; tranche 1 buys the first silicon for nine chips and the first approvals.
1. What exists today: any silicon, any customers?
No silicon and no customers. DG32-LITE and DG32-2DOM are taped-out RTL and hardened die, pre-silicon (preliminary datasheets, 12 Sep 2026). The DG32-LITE lockstep core closes at 55–62 MHz in post-route timing, a pre-silicon result; the datasheet specifies 50 MHz, and SKU-10's 100 MHz is a design target (SKU Blueprint, Oct 2026). The datasheets specify the 8-bit ADC as untrimmed. There are no purchase orders or letters of intent today. The demand case is that Indian buyers in metering, defence and industrial are already obliged to buy domestic; that is a thesis, not a booked order.
2. What does ₹10 Cr buy, and how will I know it worked?
It buys nine prototypes on the 26 Dec 2026 shuttle (₹2.6 Cr, about ₹0.29 Cr each), a respin reserve for about eight re-runs (₹2.5 Cr), the engineering team (₹1.0 Cr to March 2027, ₹1.5 Cr for the next 12 months), first approvals (₹1.0 Cr: SKU-6 military screening, meter certification with a partner), tools and lab (₹1.0 Cr), contingency (₹0.3 Cr) and boards (₹0.1 Cr). Source: SKU Blueprint (Oct 2026), plan targets. The milestones are: nine designs on the shuttle by 26 Dec 2026; first silicon brought up on boards; approvals started for SKU-6 and the meter SoC. The silicon return date is not stated in any source document, so no date is committed until ChipFoundry confirms it.
3. The Blueprint says ₹608 Cr in FY31 and the model says ₹594 Cr. Which is it?
Neither contradicts the other; they measure different things. ₹608 Cr is chip revenue alone (SKU Blueprint, Oct 2026). ₹594.3 Cr is total company revenue, of which chips are ₹45.0 Cr and Systems ₹501.9 Cr (financial model v3, Sep 2026). Both are plan targets. The model predates the Blueprint and has not taken in its ramp; a model v4 with the Blueprint ramp as its chip line is due before tranche 2.
4. When does chip revenue start, and what slows it?
The Blueprint's first chip revenue is ₹70 Cr in FY29 (Apr 2028–Mar 2029), from DG32-Max and the motor controller (plan target). Both sell into industrial markets, where customer qualification takes 6–12 months; smart meters take 12–18 months (BIS IS 16444 plus a utility tender). Automotive and defence take 18–36 months (AEC-Q100 and design-in; MIL screening and vendor listing), which is why the automotive group carries only ₹18 Cr and the defence group ₹28 Cr of the FY31 ramp. Approval times are estimates from the Blueprint's approval table. The FY29 start also depends on first silicon working, which no one has measured yet.
5. How much capital does this take in total, and do the margins hold?
Development cost for all eleven chips is ₹41.7–91.2 Cr (estimate, SKU Blueprint, Oct 2026). The Blueprint's two tranches total ₹50 Cr, which covers the low case; the high case needs more. The September model raises ₹55 Cr (₹45 Cr equity plus a ₹10 Cr CGTMSE-backed loan) and its closing cash bottoms at ₹10.1 Cr at end FY29 (plan target). On margin, the Blueprint costs four chips at 53–82% gross margin: for example the voltage supervisor at $0.09–0.17 to make against $0.20–0.80 prices, and DG32-Max at $1.30–2.30 against $3–8 (estimates, no silicon yet). The model's FY31 gross margin of 84% is above that range.
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