44 signals in a 9 × 9 mm package.

The package, interfaces and supply requirements set the integration work for the equipment maker. Some choices are defined today; final electrical limits depend on silicon characterisation.

9 × 9 mm, 16 pads a side at 0.5 mm pitch, pin 1 upper left and numbered counter-clockwise. Pads are lit by side group: the pin-by-pin map awaits the foundry’s bond-diagram confirmation.

Eleven signal groups share 44 pins, set between supplies and grounds on every side.

Pick a side to light its pads. The groups sit between supplies and grounds on every side.

PWM AH, AL, BH, BL, CH, CL · PWM trigger · Encoder A, B, Z · Hall A, B · ADC −

TOP · PINS 49–64I²C, GPIO and safety

SPI MISO, CSN · I²C · GPIO0–2 · FAULT_N · supply-good × 2 · ADC +

LEFT · PINS 1–16Motor and position

PWM AH, AL, BH, BL, CH, CL · PWM trigger · Encoder A, B, Z · Hall A, B · ADC −

RIGHT · PINS 33–48Flash and serial

QSPI CSN0, IO0–3, CSN1 · UART0 TX/RX · UART1 TX/RX · SPI SCLK, MOSI

BOTTOM · PINS 17–32Debug, clock and reset

JTAG × 4 · CLK · RST_N and resetb · Hall C · QSPI clock

Supplies and grounds sit between the groups on every side. Pin 1 (dot) is upper left, numbered counter-clockwise. Pin map awaiting the foundry’s bond-diagram confirmation.

Signal pins by function
Function	Signals	Pins
Motor PWM	AH, AL, BH, BL, CH, CL + ADC trigger	7
Position sensing	Encoder A, B, Z · Hall A, B, C	6
Analog	SAR ADC VINP, VINN (0–1.8 V)	2
QSPI flash	Clock, 4 data, 2 chip selects	7
Serial	UART0 TX/RX · UART1 TX/RX	4
SPI	SCLK, MOSI, MISO, CSN	4
I²C	SCL, SDA (open-drain)	2
GPIO	GPIO0–2	3
Safety	FAULT_N · 2 × supply-good inputs	3
JTAG	TCK, TMS, TDI, TDO	4
Clock & reset	CLK, RST_N	2
Total	Signal pins	44

PACKAGEQFN-64

BODY9 × 9 mm

PITCH0.5 mm

EXPOSED PADDLEGround

CORE SUPPLY1.8 V

I/O SUPPLY3.3 V

One rail powers
all of the logic.

The parts of the datasheet a design commits to first: which supplies exist, the order they come up, and the single clock the whole die runs from.

One rail powers all logic

Every milliamp of dynamic and leakage current for the logic, SRAM and ADC comes from the 1.8 V core rail. The 3.3 V ring supplies the pads and their protection.

WHYThe other user supply domains are unused and held at nominal only to keep the pad ring’s protection structures biased.

Sequencing

3.3 V comes up before, or together with, 1.8 V.

WHYThe pad ring must be powered before the core drives it.

Clock and reset

One 3.3 V CMOS clock input at the 50 MHz design target, used as delivered: there is no on-die PLL. Two active-low reset inputs are combined on the die with the power-on reset.

WHYAny one of them resets the core, so a design can use either input.

Every electrical limit
is a nominal until silicon.

130 nm process nominals for each supply domain, the same on DG32-LITE and DG32-2DOM. First-silicon characterisation replaces this section.

Recommended operating conditions
Parameter	Min	Typ	Max	Note
Core supply	1.71 V	1.8 V	1.89 V	±5%; powers all logic, SRAM and the ADC
I/O supply	3.0 V	3.3 V	3.6 V	3.3 V CMOS pad ring
Core clock	–	50 MHz	~55 MHz	Lockstep core reaches ~55–62 MHz post-route
ADC input	0 V	–	1.8 V	Differential, core-supply domain
Junction temperature	–	25 °C	–	Range set at characterisation

Absolute maximum ratings
Parameter	Min	Max
Core supply	−0.3 V	1.95 V
I/O supply	−0.3 V	3.63 V
Any digital pad	−0.3 V	I/O supply + 0.3 V
Analog pad	−0.3 V	core supply + 0.3 V
Storage temperature	−40 °C	125 °C (target)

Power: ~0.43 W at 50 MHz, a vectorless tool estimate at 25 °C and 1.8 V, not a measurement.

What a design can lock now,
and what waits for silicon.

Fixed now

QFN-64 body, 9 × 9 mm, 0.5 mm pitch, exposed ground paddle
Pin 1 upper left, numbered counter-clockwise
44 signals in eleven functional groups
1.8 V core and 3.3 V I/O supplies, one 50 MHz clock, self-boot from flash

Preliminary

The pin map, awaiting the foundry’s bond-diagram confirmation
Every electrical limit: process nominals until first-silicon characterisation
Junction-temperature range, set at characterisation

Preliminary pin map. Register maps, the memory map and board-level design rules are in the engineering datasheet, not on this site.