SKU-1 · 130 nm BCD BLDC motor controller
SKU-1 puts motor control and gate drive on one 130 nm BCD chip, for motor supplies up to 120 V.
Every figure on this page is a design target unless marked otherwise.
- High-voltage rail
- 5 V to 120 V motor supply; on-die gate drive to about 20 V, external power switches above
- Control engine
- Hardware PID under 1 µs, CORDIC, inverse Clarke and Park
- PWM
- Seven channels to 200 kHz (six-switch bridge plus one auxiliary)
SKU-1 puts motor control and gate drive on one 130 nm BCD chip, for motor supplies up to 120 V.
A controller and gate driver usually require separate parts. SKU-1 proposes to combine those roles for motors, appliances and actuators.
- Job
- Control a brushless motor and drive its power stage.
- Replaces
- A DRV83xx-class gate driver plus an external MCU, collapsed onto one die with runtime star or delta selection; in fans and appliances, the imported motor-control MCU on every BLDC board.
- Status
- RTL ready; analog gate-drive and sensing circuits designed and simulated. First multi-project wafer run, cycle 1; a cost-down cut for fans and appliances is a second tape-out on the same RTL.
The business case for SKU-1
Choose the drive by its operating environment and required response, then assess whether integration reduces the complexity of your product.
What it replaces
A DRV83xx-class gate driver plus an external MCU, collapsed onto one die with runtime star or delta selection; in fans and appliances, the imported motor-control MCU on every BLDC board.
Customer opportunity
Captive: every ASWA actuator joint and every D100 module. Commercial: EV and industrial drives, BLDC ceiling fans, inverter appliances, drones and robot actuators.
Policy and demand
The defence procurement list (PIL-5) names a BLDC motor with encoder for the ATGM programme. The BEE star rating is moving ceiling fans to BLDC, inverter compressors are already the norm in new air conditioners, and drone and robotics programmes add country-of-origin rules.
The delivery trade-off
Up to about 20 V the gate drive, regulator and processor share one die; higher rails, up to 120 V, use external power switches the chip drives. An advanced node would push even the gate drive back onto the board. The fan-and-appliance cut drops the buck-boost and most of the memory.
What SKU-1 claims, what it is worth, and what gates it.
The following mechanisms explain the proposed customer benefit. Each still needs to be validated in the complete product.
SKU-1 puts motor control and gate drive on one 130 nm BCD chip, for motor supplies up to 120 V.
A controller and gate driver usually require separate parts. SKU-1 proposes to combine those roles for motors, appliances and actuators.
One chip replaces the separate controller and gate driver.
Choose the drive by its operating environment and required response, then assess whether integration reduces the complexity of your product.
The datapath is FPGA-validated at 81.25 MHz; the 120 V power stage waits for silicon.
Validate the complete power stage before treating a component reduction as a production benefit.
Architecture targets, not datasheet values.
Every figure is a design target stated in the SKU Blueprint, page 10. None is a measurement of manufactured silicon.
- 120 VTop of the motor supply it controls
- < 1 µsHardware PID loop
- 200 kHzPWM, seven channels
Detailed architecture and specifications
- Process
- 130 nm BCD / high-voltage CMOS
- High-voltage rail
- 5 V to 120 V motor supply; on-die gate drive to about 20 V, external power switches above
- Processor
- DGridRiscV (RV32IM) at 100 MHz; FPGA prototype at 81.25 MHz
- Memory
- Secrets in on-chip ReRAM; firmware in external flash
- Conversion
- 16-bit synchronised ADC, three current-sense amplifiers
- Control engine
- Hardware PID under 1 µs, CORDIC, inverse Clarke and Park
- PWM
- Seven channels to 200 kHz (six-switch bridge plus one auxiliary)
- Versions
- Full version for traction, drives, drones and robots; cost-down cut for fans and appliances (second tape-out, same RTL)
- Process
- 130 nm BCD
- Maturity
- Architecture scope
- Designed toward
- AEC-Q100 Grade 0 · ISO 26262 ASIL-B/C · UL94
- Source
- SKU Blueprint, October 2026, page 10
Standards the architecture is designed toward. No DeepGrid part holds a certification or qualification today.
System architecture, signal flow and engineering references
Marker ①: The host takes commands but stays out of the loop
Speed, torque, halt, brake and ramp commands arrive at Host interfaces and the DGridRiscV core, a 100 MHz RISC-V with SRAM, ReRAM for secrets and Timers · WDT · CCU beside it; firmware sits in external flash. The core configures the loop and supervises it over the AXI bus. It does not sit in the loop, so firmware timing never decides when the gates switch.
Host · control plane
Marker ②: The torque command becomes phase drive in hardware
In the Field-oriented control datapath, the PID tuner sets the correction, Rect → polar turns it into magnitude and angle with a CORDIC, d,q → 3-phase applies inverse Park and Clarke, and Sine / trapezoid picks sinusoidal or six-step drive. Because the loop is hardware, its latency is fixed, with a target under 1 µs.
Field-oriented control datapath
Marker ③: PWM switches three half-bridges on a motor supply up to 120 V
PWM × 7 drives the Pre-drivers R / Y / B: six channels for the bridge and one auxiliary, up to 200 kHz. The chip controls the motor supply from 5 V to 120 V: up to about 20 V the gate drive sits on the die, and above it the chip drives external power switches. Star / delta selects the winding at runtime.
Power path
Marker ④: Current and angle feedback closes the loop on the die
Hall / quad / enc inputs feed Angle (ω) for rotor position and speed. iR iY iB rebuild and Instant current reconstruct the three phase currents, which CSA × 3 amplify and the 16-bit ADC digitises in the Mixed signal zone. The feedback returns to the PID tuner, so the loop closes without a round trip through firmware.
Sensor + feedbackMixed signal
Marker F: A fault shuts the gates and the trip stays latched
Protection watches for thermal, overcurrent and overvoltage faults. On any of them it shuts the gate drive at the Pre-drivers R / Y / B, and the shutdown is latched: it holds after the fault passes instead of switching the bridge back on by itself. Above it, the watchdog in Timers · WDT · CCU supervises the processor.
Power pathHost · control plane
Numbered markers
- ①Marker ①: Speed, torque, halt and brake commands reach the host.
- ②Marker ②: The datapath turns the torque command into phase drive: PID, CORDIC, inverse Park and Clarke, waveform lookup.
- ③Marker ③: PWM drives the three half-bridge pre-drivers.
- ④Marker ④: Current and angle feedback closes the PID loop.
- FMarker F: A thermal, overcurrent or overvoltage fault shuts the gates and latches.
Block responsibilities
- Host · control plane
A DGridRiscV core with timers and watchdog, SRAM and ReRAM, and the host interfaces. It sets the loop up and supervises it.
Why The processor configures and supervises; it does not sit in the loop.
Guide: Host · control plane- Mixed signal
A 16-bit ADC for phase, bus and temperature, four reference DACs, an on-die temperature sensor and three current-sense amplifiers.
Guide: Mixed signal- Power path
A buck-boost converter, seven PWM channels, three half-bridge pre-drivers, latched protection and runtime star or delta winding selection.
Why Up to about 20 V the gate drive sits on the BCD die beside the logic; above it, up to 120 V, the chip drives external power switches.
Guide: Power path- Field-oriented control datapath
A hardware PID tuner, a CORDIC rectangular-to-polar stage, inverse Park and Clarke, and sine or trapezoid lookup: torque command in, phase drive out.
Why The loop runs in hardware, so its latency is fixed and stays under 1 µs.
Guide: Field-oriented control datapath- Sensor + feedback
Hall, quadrature or encoder inputs give rotor angle and speed; the three phase currents are rebuilt, amplified and digitised.
Guide: Sensor + feedback
Primary sources
- SKU-1 architecture guideEvery block group, the data flows and the design targets.Opens in the site
- SKU Blueprint, October 2026SKU-1: what it replaces, who uses it, its status and its architecture diagram.PDF · 46 pages
4 integration and validation references
- Field Orientated Control of 3-Phase AC-Motors (TI BPRA073)The Clarke and Park transforms, the PI regulator and PWM behind the control datapath.Texas Instruments · PDF
- The CORDIC trigonometric computing techniqueVolder, IRE Transactions on Electronic Computers, 1959: the shift-and-add method behind the CORDIC block.IEEE · DOI
- RISC-V ratified specificationsThe instruction set the DGridRiscV cores execute.RISC-V International
- Arm AMBA specifications, including AXI and AHBThe bus protocol family the on-chip bus is modelled on.Arm
Background reading explains the general technique each block uses. None of it describes this part or implies its certification.
Architecture from the SKU Blueprint, page 10. A functional view, not a floorplan.
7 questions SKU-1 has to answer before it can be relied on.
The Blueprint’s design and status notes raise these. Each is a question silicon, test or layout has to answer before SKU-1 can be relied on.
The motor supply spans 5 V to 120 V.Physics
Up to about 20 V the gate drive, regulator and processor share one die; higher rails use external power switches the chip drives. An advanced node would push even the gate drive back onto the board.
A 16-bit ADC shares the die with a switching half-bridge.Physics
Fast switching edges couple into the substrate, so the analog section needs guard rings and separate grounds.
The control loop must close in under a microsecond.Physics
PID, CORDIC and the Clarke and Park transforms run as a hardware datapath, not as firmware.
Substrate isolationOpen
Which guard-ring and deep-trench structures keep fast switching edges from the on-die gate drive out of the 16-bit ADC?
Loop deadline under bus loadOpen
Does the CORDIC datapath still meet its 1 µs deadline while the processor runs CAN-FD traffic over the same bus?
ReRAM at temperatureOpen
Retention falls quickly above 125 °C junction. What ECC and scrubbing keep stored parameters intact in continuous operation?
Shoot-throughOpen
How fine is dead-time insertion, and does it hold as gate thresholds drift with temperature?
An architecture, with its evidence named.
- Strongest evidence
- FPGA-validated: the motor control datapath runs as circuit code on an Artix-7 at 81.25 MHz.
- Development status
- RTL ready; analog gate-drive and sensing circuits designed and simulated. First multi-project wafer run, cycle 1; a cost-down cut for fans and appliances is a second tape-out on the same RTL.
The high-voltage motor-controller architecture is distinct from DG32’s low-voltage safety MCU.
How every figure on this site was obtainedThe systems it goes into, and the parts beside it.
Motor topology, bus voltage, gate-drive needs and protection requirements.
Parts beside it
Read the source behind every figure.
Each document opens inside the site at the cited section; the PDF is the edition of record.
- SKU Blueprint, October 2026 (11 SKUs + D100)SKU-1, page 10 · source of recordPDF · 46 pages
- Mature-Node Silicon for India’s Defence (Whitepaper v3)Evidence for this partPDF · 71 pages
Design files
Bring the socket. We will tell you what SKU-1 has to prove for it.
Send the platform, voltage and power environment, interfaces and qualification needs. The reply names what is architecture, what is evidence and what would have to be tested.