The SKU portfolio, chip by chip.
Eleven chips from the October SKU Blueprint: readiness, prototype slot, plan line, revenue ramp, approval time, development and unit cost, each panel linked to the data behind it. Plan targets, not results.
Three chips carry 89 % of the FY31 ramp; approval time, not market size, sets the pace for the rest.
Nine of eleven chips go on the December 2026 shuttle, and their plan lines total ₹1,000 Cr at full rate. On the Blueprint's approval times the ramp reaches ₹608 Cr in FY31, 61 % of that; SKU-1, SKU-2, SKU-10 carry most of it, because they sell into industrial and metering markets, which approve soonest.
Plan targets, not results. Every figure is from the SKU Blueprint, October 2026 (PDF) or the DG32 preliminary datasheets. A plan line is what a chip can carry at full rate; the ramp is what the Blueprint expects year by year. Nothing here is a purchase order.
Reading the team's live tables; until then, the copy checked at the last site build. The tables are public: open the SKU table. The reading for investors and buyers is in the brief.
Revenue, capital and qualification priorities
- 89 %Three chips carry the FY31 ramp
SKU-1, SKU-2, SKU-10: ₹541 Cr of the chips' ₹609 Cr in FY31. The other eight share the rest.
SKU Blueprint, Oct 2026 · plan targets - 61 %FY31 reaches part of the plan
₹608 Cr in FY31 against ₹1,000 Cr of plan lines at full rate; ₹1,000 Cr in FY31 is the Blueprint's stretch target.
SKU Blueprint, Oct 2026 · plan targets - 9 of 11First silicon this year
On the ChipFoundry December 2026 shuttle. Not on it: SKU-7, SKU-11.
SKU Blueprint, Oct 2026 · schedule - 6–36 moApproval sets the pace
Automotive, defence, space take up to 36 months after silicon; industrial, consumer, drones 6–12.
SKU Blueprint, Oct 2026 · estimates
Revenue opportunity by product
Only three chips reach 70 % of their plan line by FY31 (SKU-1, SKU-2, SKU-10); the other eight are at 40 % or less.
- Plan line
- FY31 ramp
| Chip | Process | Readiness | Dec 2026 shuttle | Plan line | FY31 ramp | Market, ₹ Cr | Market verdict |
|---|---|---|---|---|---|---|---|
| SKU-1 BLDC Motor Controller | 130 nm, 100 MHz | RTL + analog schematics ready | Yes (MPW cycle 1) | 320 | 256 | 337–2,719 | Plausible |
| SKU-2 Smart-Meter SoC | 130 nm, 100 MHz | RTL + analog schematics ready | Yes (MPW cycle 1) | 250 | 175 | 273–1,794 | Plausible |
| SKU-3 Hi-Rel PMIC | 130 nm first, 180 nm production | RTL + analog schematics ready | Yes | 40 | 12 | 22–358 | Plausible |
| SKU-4 Lockstep MCU | 130 nm, 100 MHz | RTL ready | Yes | 40 | 4 | 114–1,145 | Conservative |
| SKU-5 Interface Transceiver | 130 nm | RTL + analog schematics ready | Yes (MPW cycle 2) | 45 | 14 | 76–859 | Conservative |
| SKU-6 Voltage Supervisor | 130 nm first, 180 nm production | RTL + analog schematics ready | Yes (MPW cycle 1) | 40 | 16 | 58–658 | Plausible |
| SKU-7 4D Radar RF | SiGe front end + 130 nm CMOS | digital RTL ready | No | 35 | 4 | 76–1,192 | Conservative |
| SKU-8 Display Driver | 130 nm high-voltage CMOS | RTL + analog schematics ready | Yes | 20 | 8 | 14–229 | Plausible |
| SKU-9 SDV Zonal Gateway | 130 nm, 100 MHz | digital RTL ready | Yes | 60 | 6 | 57–763 | Plausible |
| SKU-10 DG32-Max Secure MCU | 130 nm, 100 MHz | RTL ready | Yes (ChipFoundry OpenFrame, December 2026) | 110 | 110 | 229–1,908 | Conservative |
| SKU-11 SOH-Aware BMS Controller | 130 nm, 100 MHz | specification | No (MPW slot not yet assigned) | 40 | 4 | 57–572 | Plausible |
| D100 D100 Drone SoC | 28 nm | – | – | – | – | – | – |
Plan lines sum to ₹1,000 Cr (checked at build). SKU-11 SOH-Aware BMS Controller is still at specification; D100 is Track B, on 28 nm, with no plan line yet. Clock is the product target, not a measurement. Source: skus.csv.
The ramp grows from ₹70 Cr in FY29 to ₹948 Cr in FY33; DG32-Max, motor controller is the largest group.
- DG32-Max, motor controller
- Smart meter, transceiver, display
- Supervisor, PMIC (defence first)
- Automotive: SKU-4, 7, 9, 11
| Chip group | FY29 | FY30 | FY31 | FY32 | FY33 |
|---|---|---|---|---|---|
| DG32-Max, motor controller | 70 | 210 | 366 | 430 | 430 |
| Smart meter, transceiver, display | – | 82 | 196 | 302 | 315 |
| Supervisor, PMIC (defence first) | – | 4 | 28 | 60 | 80 |
| Automotive: SKU-4, 7, 9, 11 | – | – | 18 | 52 | 122 |
| Total, as stated | 70 | 296 | 608 | 844 | 948 |
Column labels are the Blueprint's stated totals; where the groups sum one away from a total, that is rounding in the source. Source: ramp.csv.
Qualification lead times govern revenue timing
Revenue waits on approvals of 6 to 36 months; automotive, defence, space take longest.
What each market requires before it buys in volume, and how long that takes. Source: approvals.csv.
Development capital and unit economics
Nine prototypes, Respin reserve, Engineering team take 76 % of the ₹10 Cr first tranche.
| Use | ₹ Cr | What it delivers |
|---|---|---|
| Nine prototypes, December 2026 shuttle | 2.6 | SKU-1 to SKU-6 and SKU-8 to SKU-10 at about ₹0.29 Cr each ($15 K slot + $15 K IP and other costs) |
| Respin reserve | 2.5 | About eight prototype re-runs at ₹0.29 Cr each, held inside tranche 1 |
| Engineering team | 2.5 | ₹1.0 Cr to March 2027, ₹1.5 Cr for the following 12 months; tranche 2 grows |
| First approvals | 1.0 | Military screening of SKU-6; meter certification work with a partner |
| Design tools and lab | 1.0 | EDA licences, test equipment |
| Contingency | 0.3 | General contingency |
| Bring-up and evaluation boards | 0.1 | Respins come from contingency |
| Total | 10.0 |
Uses sum to ₹10 Cr (checked at build). Source: tranche1-uses.csv.
Not the same plan as the Business plan page. That page shows the September financial model: it raises ₹45 Cr (pre-Series A equity round) and ₹10 Cr (cGTMSE-backed term loan), and expects ₹594 Cr of whole-company revenue in FY31. This October Blueprint funds the chips in tranches, starting with the ₹10 Cr above, and expects ₹608 Cr from these chips in FY31. Read each figure with its own document. Business plan
SKU-7 4D Radar RF costs the most to develop, up to ₹12.8 Cr; the others need ₹2.1 Cr–11.1 Cr each.
Development cost sums to ₹41.7 Cr–₹91.2 Cr across the eleven chips (checked at build). The addressable market per chip runs up to ₹2,719 Cr; see the table above. Source: skus.csv.
At volume, the four costed chips keep 53–82 % of their price as gross margin.
| Chip | Die, mm² | Package | Unit cost | Price | Gross margin |
|---|---|---|---|---|---|
| Voltage supervisor | 1 | SOT-23 | $0.09–$0.17 | $0.20–$0.80 | 66–82 % at $0.50 |
| Interface transceiver | 2 | SOIC-8 | $0.17–$0.30 | $0.40–$1.50 | 68–82 % at $0.95 |
| Motor controller, fan cut | 3 | QFN-24 | $0.27–$0.47 | $0.50–$1.50 | 53–73 % at $1.00 |
| DG32-Max | 15 | QFN-64 | $1.30–$2.30 | $3.00–$8.00 | 58–76 % at $5.50 |
Cost to make at volume, and the gross margin at the price point the Blueprint names. Prototype costs are quoted; mask and qualification costs are planning estimates. Source: unit-cost.csv.
DG32 specifications and product maturity
The two DG32 dies share a package, a process and their memory; DG32-2DOM adds an attention engine on its own clock.
| Specification | DG32-LITE (SKU-4) | DG32-2DOM |
|---|---|---|
| Core | 2x rv32imc lockstep | 2x rv32imc + INT8 attn |
| Clock | 50 MHz | 50 / 114 MHz |
| SRAM | 32 KB (no ECC) | 32 KB (no ECC) |
| Boot ROM | 64 KB | 64 KB |
| ADC | 8-bit differential SAR, untrimmed on this silicon | 8-bit differential SAR, untrimmed on this silicon |
| Supply | 1.8 V core, 3.3 V I/O | 1.8 V core, 3.3 V I/O |
| Package | QFN-64, 9x9 mm | QFN-64, 9x9 mm |
| Process | sky130A 130 nm | sky130A 130 nm |
| Status | pre-silicon, taped-out RTL and hardened die | pre-silicon, taped-out RTL and hardened die |
DG32-2DOM: attention variant of DG32-LITE; no SKU number in the Blueprint. Preliminary datasheets; 50 MHz is the CPU-domain design target, set by the lockstep core’s measured 55–62 MHz post-route. Source: dg32-specs.csv.
Investment assumptions and product-scope reconciliation
Current product scope and financial assumptions need dated approval.
| Document | Where | Version | Pages | Status | Note |
|---|---|---|---|---|---|
| SKU Blueprint, October 2026 | published | Oct 2026 | 46 | current | Text-identical to the Downloads copy. Pages are marked CONFIDENTIAL. |
| Master whitepaper v3 | published | 5 Sep 2026 | 71 | superseded in part | The Blueprint is newer on chip count, clock, orders, plan and funding. Marked "CONFIDENTIAL · Not for distribution"; prints personal contact details on page 2. |
| DG32-LITE preliminary datasheet | published | 12 Sep 2026 | 12 | current | States the ADC runs untrimmed on this silicon. |
| DG32-2DOM preliminary datasheet | published | 12 Sep 2026 9:07 | 12 | current (replaced 12 Oct 2026) | The published copy was the 08:34 version, which said per-die ADC trim is a bring-up step. Replaced with the 09:07 version (ADC untrimmed). Only page 10 differs. |
| DG32 QFN-64 datasheets, both parts | published | rebuilt 12 Oct 2026 | 24 | current (rebuilt 12 Oct 2026) | DG32-LITE (pages 1-12) plus the current DG32-2DOM (pages 13-24). Its 2DOM half had contradicted its LITE half on ADC trim. |
| DG32-2DOM system architecture | published | 12 Sep 2026 evening | 24 | current | The newer 24-page version: adds the measured block-area breakdown and the AVIP bearing-fault application. |
| DG32-AI 30 use cases | published | 11 Sep 2026 | 12 | current | Byte-identical to Downloads DG32-LITE_Base_Variant_Use_Cases.pdf. |
| DShot RX block spec | published | 13 Sep 2026 | 8 | current | Byte-identical to Downloads DG32_dgrid_dshot_rx_spec_draft1.pdf (a draft). |
| Downloads: DG32-2DOM_Datasheet.pdf | local | 12 Sep 2026 8:34 | 12 | stale | Superseded by DG32-2DOM_Datasheet-1.pdf (ADC note). |
| Downloads: DG32-2DOM_Block_Architecture.pdf | local | 12 Sep 2026 morning | 22 | stale | Superseded by the 24-page -1/-2 copies, which are identical to each other. |
| Downloads: DG32-LITE_Datasheet-2/-3, DG32-2DOM_vs_STM32 (+ -2) | local | 12 Sep 2026 | – | duplicates | Byte-identical pairs. |
Which copy of each document is current: the published downloads, and the local copies they were checked against. Source: documents.csv.
Unresolved product and investment assumptions: 0 open, 9 fixed, 1 decided by the owner.
| Topic | One source says | Another says | Status |
|---|---|---|---|
| ADC trim (DG32-2DOM) | 2DOM datasheet 08:34 (was published): per-die trim is a bring-up step | 2DOM datasheet 09:07, system architecture, LITE datasheet: trim has no effect on this silicon; the ADC runs untrimmed | fixed 12 Oct 2026 |
| ADC trim inside one document | QFN-64 combined, DG32-LITE half: untrimmed | QFN-64 combined, DG32-2DOM half: per-die trim is a bring-up step | fixed 12 Oct 2026 (rebuilt) |
| Page count | detail-content.ts document list: 28 pages | deepgrid-datasheets-qfn64.pdf: 24 pages | fixed 12 Oct 2026 |
| Processor clock | Whitepaper v3 (Sep): 200 MHz target; timing analysis not yet published | Blueprint (Oct) / DG32-LITE datasheet: 100 MHz product / 50 MHz die (lockstep core 55-62 MHz post-route) | fixed 12 Oct 2026: every whitepaper listing now says the October Blueprint is newer on the clock |
| SKU-10 clock | Site SKU-10 page: a 100 MHz lockstep pair on SKY130 | DG32-LITE post-route timing: lockstep core reaches 55-62 MHz on sky130 | fixed 12 Oct 2026: the SKU-10 page labels 100 MHz a design target and states the measured 55-62 MHz |
| Chip count | Whitepaper v3: ten chips | Blueprint: eleven SKUs plus the D100 Track B | fixed 12 Oct 2026: every whitepaper listing now says the Blueprint is newer on chip count |
| Orders | Whitepaper v3: a figure this site withholds as misdescribed | Blueprint / site Evidence page: no purchase orders or letters of intent / a figure this site withholds as misdescribed | fixed 12 Oct 2026: a figure this site withholds as misdescribed |
| Raise | Whitepaper v3: Rs 10 Cr angel/seed | Blueprint / financial model (corrected v3): Rs 10 Cr + Rs 40 Cr tranches / Rs 45 Cr equity + Rs 10 Cr loan | fixed 12 Oct 2026: /portfolio sets the Blueprint tranches beside the model on /plan, each with its own document |
| FY31 revenue | Whitepaper v3 (and /company): Rs 1,000 Cr | Blueprint / financial model (and /plan): Rs 610 Cr (Rs 1,000 Cr at full rate) / Rs 594 Cr (whole company) | fixed 12 Oct 2026: /plan and /portfolio each show their figure with its scope and date |
| Confidential marking | Whitepaper v3, Blueprint: CONFIDENTIAL (whitepaper: Not for distribution) | v11/v12 public downloads: published without a login | decided 12 Oct 2026: kept published as the owner chose; the documents are left as authored |
| Ramp rounding | Blueprint ramp table: FY33 total Rs 948 Cr | sum of its groups: Rs 947 Cr | info: rounding in the source |
Each row is one claim two sources state differently, and what was done about it. Figures this site withholds are not repeated. Source: conflicts.csv.
DeepGrid chips earn revenue inside equipment makers’ systems.
Explore the proposed product roles, then examine their architecture, validation and qualification requirements.
