Deepgrid Semi
DG32 · LOCKSTEP RISC-V MOTOR-CONTROL SILICONPRE-SILICON · ENGINEERING EVIDENCE
Request a discussion

Silicon for motion,
power and sensing.

DeepGrid is developing silicon for motion, power, sensing and communications. Explore the product architectures, their role in your equipment, and the evidence needed before adoption.

Request a discussion Explore the products
Pre-silicon portfolio

Architecture and engineering evidence today. Manufactured-silicon results and qualification still ahead.

DeepGrid portfolio concept with separate motor-drive, metering, radar and zonal-interface assemblies
Motion, metering, sensing and zonal interfaces. New DeepGrid portfolio concept · concept illustration, not a product photograph or deployment evidence. DeepGrid silicon remains pre-silicon.

Twelve architectures.
Two carry engineering evidence today.

Compare the customer problem each product addresses, its role in the equipment and its current evidence. Product breadth does not imply equal readiness.

12 architectures · Pre-silicon portfolio

SKU-1BLDC motor controllerControl a brushless motor and drive its power stage.130 nm BCDArchitecture scopeSKU-4DG32 safety MCUMake a control-core disagreement observable at the hardware fault output.130 nm CMOSPre-silicon engineering evidenceSKU-2Smart-meter SoCMeasure electrical energy and preserve metering state when mains power is absent.130 nm CMOSArchitecture scopeSKU-3High-reliability PMICTurn an equipment power bus into sequenced board supplies.SCL 180 nm BCD; sky130 prototypeArchitecture scopeSKU-6Quad-rail supervisorDetect unsafe supply conditions and latch a fault.SCL 180 nm CMOS; sky130 prototypeArchitecture scopeSKU-5Interface transceiverConnect digital control to an electrically exposed harness.130 nm LDMOSArchitecture scopeSKU-777 GHz radarConvert radio-frequency reflections into range and motion information.IHP SiGe + 130 nm CMOSArchitecture scopeSKU-8Rugged display driverTranslate digital image data into panel drive signals.130 nm high-voltage CMOSArchitecture scopeSKU-9Zonal controller & gatewayBring power distribution and network connections into a vehicle zone.130 nm CMOS and BCDArchitecture scopeSKU-10DG32-Max secure MCUBoot only signed firmware on one chip, without a separate secure element.130 nm CMOS (SKY130)Pre-silicon engineering evidenceSKU-11SOH-aware BMS controllerRun a lithium battery pack safely and estimate its state of health on the chip.130 nm CMOS (SKY130)Architecture scopeD100Drone SoCSeparate flight safety from higher-level perception compute.28 nm; 130 nm failsafe islandArchitecture scope

Hardware fault response in 39 cycles.

In simulation, DG32 detects a processor disagreement and trigger a protective response without waiting for application software. The important decision is whether that response meets the needs of the complete machine.

Representative assembly with visible motor, bridge power stage, controller package and electrical interfaces
MotionSKU-1 + DG32
PowerSKU-3 + SKU-6
InterfacesSKU-5
ControllerDG32 · QFN-64
Package opened · functional view below
Illustrative lid separation; not a physical die layout.
Bridge drive enabledMotor rotation · illustrative
Representative system · illustrative architecture
FUNCTIONAL VIEW / NOT A DIE LAYOUT
MAINresults →CHECKER2-cycle skewcompare →Comparator
Sticky latch→FAULT_NHIGH→Gate driverENABLED
DG32 functional safety path
  1. 01MAIN executesResults agree
  2. 02CHECKER follows · 2-cycle skewResults agree
  3. 03Comparator detects mismatchWaiting for mismatch
  4. 04Sticky fault latch records causeWaiting for mismatch
  5. 05FAULT_N asserts lowWaiting for mismatch
  6. 06Gate-driver disabledWaiting for mismatch

Normal operation: MAIN and the delayed CHECKER results agree. Inject a mismatch to follow the response.

Interactive explanation, not an executable silicon simulation. The animation is slowed for reading; reported fault latency: 39 cycles · simulated. The complete causal path remains readable without WebGL or motion.
39 cycles
Injected-fault response · simulated

The complete reported path differs from the checker’s two-cycle execution skew. Hardware lockstep is a mechanism, not a functional-safety certificate.

Read the fault-path source
Inspect fault causes and reset behaviour

Control, power and interfaces
in one system.

A product earns its place by solving a system problem. Explore how control, power and interfaces contribute to the equipment, and which responsibilities remain outside the chip.

Explore system applications
SKU-1 Motor control original DeepGrid architecture diagram
SKU-1 · The control engine and the power stage, in one architecture.
Original DeepGrid architecture diagram · pre-silicon design. Explore this part
Representative assembly with visible motor, bridge power stage, controller package and electrical interfaces
MotionSKU-1 + DG32
PowerSKU-3 + SKU-6
InterfacesSKU-5
ControllerDG32 · QFN-64
Bridge drive enabled
Representative system · illustrative architecture
System

A representative assembly. Select a function to locate its sockets.

Product labels identify roles, not a validated reference board. Sensing is a conceptual socket, not an assigned component in this illustration.

DG32 physical design.
Silicon validation comes next.

The DeepGrid Silicon Engine capture shows the DG32-LITE layout. It records pre-silicon design work; manufactured-silicon measurements and product qualification are separate milestones.

Inspect the complete layout image
DG32-LITE layout capture showing routed interconnect and functional regions in the DeepGrid Silicon Engine
Original DeepGrid layout capture · pre-silicon physical design, not a product photograph.

Pre-silicon validation.
Qualification still ahead.

Architecture breadth, engineering work and commercial readiness answer different questions. Evaluate each on its own evidence.

Review evidence & withheld claims

Current engineering and commercial basis

  • Portfolio architectures and dated SKU Blueprint tables
  • DG32 simulation, implementation and post-route records
  • Named approval routes and estimated unit costs

Silicon, qualification and customer milestones

  • Returned-silicon measurements and confirmed sample dates
  • Qualification and application-specific validation
  • Purchase orders, letters of intent and reconciled financial assumptions

₹10 Cr funds first silicon for nine chips
on the December 2026 shuttle.

The Blueprint allocates ₹10 Cr in tranche 1 to first-silicon work. Its December shuttle plan includes 9 designs. This is a prototype milestone, with qualification and full development still ahead.

Review the funding brief

SKU Blueprint, October 2026 · planned allocations, not capital received or silicon results.

Tranche 1 capital allocation

Nine prototypes, December 2026 shuttle
₹2.6 Cr
Respin reserve
₹2.5 Cr
Engineering team
₹2.5 Cr
First approvals
₹1 Cr
Design tools and lab
₹1 Cr
Contingency
₹0.3 Cr
Bring-up and evaluation boards
₹0.1 Cr

The September model and October Blueprint use different revenue scopes. Read their reconciliation before comparing headline totals.

Compare the two plans

Portfolio discussions, partner evaluations
and data-room access start here.

Request a portfolio discussion, strategic-partner evaluation or data-room access. Tell us which assumptions and evidence you want to examine.

Request a discussion