SKU-5 · 130 nm LDMOS Interface transceiver
SKU-5 carries RS-485 and 8 Mbps CAN-FD on one transceiver, with a ±15 kV pin-protection target.
Every figure on this page is a design target unless marked otherwise.
- RS-485
- Half duplex, up to 256 nodes; 20 Mbps over short runs, about 83 kbps at 1.2 km
- CAN-FD
- 8 Mbps data phase, ISO 11898-2
- Protection target
- ±15 kV, stated per test standard
SKU-5 carries RS-485 and 8 Mbps CAN-FD on one transceiver, with a ±15 kV pin-protection target.
SKU-5 targets the wired interfaces used across industrial and vehicle equipment, combining bus functions on one part.
- Job
- Connect digital control to an electrically exposed harness.
- Replaces
- CAN and RS-485 interface chips from TI, ADI and Renesas, many of which defence platforms can no longer buy.
- Status
- RTL ready for the digital logic; analog line drivers designed and simulated. Prototype on the December 2026 shuttle; layout and silicon proof follow.
The business case for SKU-5
Start with the installed equipment and the replacement requirements; compatibility determines the opportunity.
What it replaces
CAN and RS-485 interface chips from TI, ADI and Renesas, many of which defence platforms can no longer buy.
Customer opportunity
One ships with every node on every industrial and vehicle bus, with screened grades for defence.
Policy and demand
Replacing obsolete parts is the quickest sale to defence PSUs: the part is already designed into a platform that can no longer buy it.
The delivery trade-off
Fine nodes are worse for this part. A 5 V-tolerant thick-oxide output stage is exactly what a line driver needs, and only mature nodes offer it.
What SKU-5 claims, what it is worth, and what gates it.
The following mechanisms explain the proposed customer benefit. Each still needs to be validated in the complete product.
SKU-5 carries RS-485 and 8 Mbps CAN-FD on one transceiver, with a ±15 kV pin-protection target.
SKU-5 targets the wired interfaces used across industrial and vehicle equipment, combining bus functions on one part.
One part covers both RS-485 and CAN-FD buses.
Start with the installed equipment and the replacement requirements; compatibility determines the opportunity.
±15 kV protection and 1.2 km RS-485 runs need tests on real wiring.
Electrical protection, wiring limits and interchangeability still require validation.
Architecture targets, not datasheet values.
Every figure is a design target stated in the SKU Blueprint, page 22. None is a measurement of manufactured silicon.
- 256RS-485 nodes
- 8 MbpsCAN-FD data phase
- ±15 kVPin protection
Detailed architecture and specifications
- Process
- 130 nm with 5 V thick-oxide LDMOS
- RS-485
- Half duplex, up to 256 nodes; 20 Mbps over short runs, about 83 kbps at 1.2 km
- CAN-FD
- 8 Mbps data phase, ISO 11898-2
- Common mode
- RS-485 −7 to +12 V (TIA/EIA-485); CAN ±12 V as drawn
- Timing
- 20 ns driver, 50 ns receiver; 70 ns loop delay
- Protection target
- ±15 kV, stated per test standard
- Standby
- Under 8 µA
- Process
- 130 nm LDMOS
- Maturity
- Architecture scope
- Designed toward
- TIA/EIA-485 · ISO 11898-2 · IEC 61000-4-2 (system level) and HBM (component level), each rated separately
- Source
- SKU Blueprint, October 2026, page 22
Standards the architecture is designed toward. No DeepGrid part holds a certification or qualification today.
System architecture, signal flow and engineering references
Bus figures use TIA/EIA-485 common mode (−7 to +12 V) and state ESD per test standard.
Marker ①: Logic IF lifts 1.8 V logic to a 5 V bus driver
On channel 1, TXD enters Logic IF, which shifts the 1.8 V core logic up to 5 V and also carries RXD, enable and standby. The logic is a thin skin around the part: every block that decides how it behaves on the wire is analog, built on the thick-oxide devices a mature 130 nm process offers.
Channel 1 · RS-485
Marker ②: The pre-driver shapes each edge to buy reach
Pre-driver slews each edge at a trimmed 3 V/ns before it reaches the Output stage. On a bus, reach and node count depend on edge timing rather than the headline bit rate, so the edge is shaped and the delay is budgeted: 20 ns for the driver, 50 ns for the receiver, 70 ns for the loop.
Channel 1 · RS-485
Marker ③: Thick-oxide outputs drive the A / B pins
Output stage is a differential push-pull on thick-oxide 5 V LDMOS, driving A / B in the Bus pins column. RS-485 runs half duplex with up to 256 nodes over a −7 to +12 V common mode, at 20 Mbps over short runs or about 83 kbps at 1.2 km: two operating points, not one.
Channel 1 · RS-485Bus pins
Marker ④: The receiver reads the bus back with 30 mV hysteresis
Receiver, a hysteresis comparator with 30 mV of hysteresis and 50 ns propagation, reads A / B back to RXD. Failsafe bias holds an idle bus at recessive and detects open, short and idle conditions, so a dead or open bus reads as a known state instead of noise that the logic could mistake for data.
Channel 1 · RS-485Bus pins
Channel 2 repeats the same path for CAN-FD
Channel 2 mirrors the same blocks across the Bus pins column: Logic IF, Pre-driver, Output stage onto CANH / CANL, then Receiver and Failsafe bias. It targets an 8 Mbps data phase with a ±12 V common mode as drawn, and its Local supply + osc adds bit-time recovery from a 40 MHz reference.
Channel 2 · CAN-FDBus pins
Every pin that leaves the board carries its own protection
ESD + EMC structures guard A / B and CANH / CANL, with a ±15 kV target rated per test standard. Fault shuts a channel down on a short or at 150 °C. Prot logic interlocks the RS-485 enable so drivers never contend, and times out a stuck CAN transmit. Local supply + osc builds 3.3 V from the 5 V bus.
Channel 1 · RS-485Channel 2 · CAN-FD
Numbered markers
- ①Marker ①: TXD enters the logic interface and is level-shifted to 5 V.
- ②Marker ②: The pre-driver shapes the edge for the output stage.
- ③Marker ③: The differential output drives the bus pins.
- ④Marker ④: The receiver reads the bus back to RXD. Channel 2 follows the same path.
Block responsibilities
- Channel 1 · RS-485 · half duplex · up to 256 nodes · −7 to +12 V CM
Logic interface with TXD, RXD and enable, a slew-shaped pre-driver, a differential push-pull output on thick-oxide LDMOS, a 30 mV-hysteresis receiver, failsafe idle bias, fault and ESD protection, a local LDO and an oscillator.
Why A 5 V-tolerant thick-oxide ring is why 130 nm suits a line driver.
Guide: Channel 1 · RS-485 · half duplex · up to 256 nodes · −7 to +12 V CM- Bus pins
RS-485 A and B, CAN CANH and CANL.
Guide: Bus pins- Channel 2 · CAN-FD · 8 Mbps data · ISO 11898-2 · ±12 V CM
The same structure for CAN-FD: logic interface, pre-driver, output stage, receiver, failsafe bias, fault and ESD protection, with a TXD timeout and bus-fault detection, and an oscillator for bit-time recovery.
Guide: Channel 2 · CAN-FD · 8 Mbps data · ISO 11898-2 · ±12 V CM
Primary sources
- SKU-5 architecture guideEvery block group, the data flows and the design targets.Opens in the site
- SKU Blueprint, October 2026SKU-5: what it replaces, who uses it, its status and its architecture diagram.PDF · 46 pages
2 integration and validation references
- The RS-485 Design Guide (TI SLLA272)Common-mode range, failsafe biasing, termination and unit loads.Texas Instruments · PDF
- Introduction to the Controller Area Network (TI SLOA101)CAN arbitration, bit timing and the physical layer of ISO 11898-2.Texas Instruments · PDF
Background reading explains the general technique each block uses. None of it describes this part or implies its certification.
Architecture from the SKU Blueprint, page 22. A functional view, not a floorplan.
6 questions SKU-5 has to answer before it can be relied on.
The Blueprint’s design and status notes raise these. Each is a question silicon, test or layout has to answer before SKU-5 can be relied on.
Bus pins face miswiring, ground shifts and electrostatic discharge.Physics
Thick-oxide 5 V LDMOS outputs and large ESD structures, which mature 130 nm offers and advanced nodes do not.
Reach and node count depend on edge timing, not headline bit rate.Physics
Trimmed slew control and a fixed propagation budget: 20 ns driver, 50 ns receiver.
A dead or open bus must read as a known state.Physics
Failsafe bias holds idle as recessive, with open, short and idle detection.
ESD on an open processOpen
Which ESD structures have silicon data at ±15 kV? This needs a dedicated test chip; it cannot be inferred from shared tiles.
Unit loadOpen
Are 256 nodes reached with eighth-unit-load receivers, and at what input impedance?
First pin-compatible targetOpen
Which discontinued interface part is the first drop-in replacement?
An architecture, with its evidence named.
- Strongest evidence
- Architecture diagram and status in the SKU Blueprint.
- Development status
- RTL ready for the digital logic; analog line drivers designed and simulated. Prototype on the December 2026 shuttle; layout and silicon proof follow.
Harness-survival and protocol requirements need device-level validation.
How every figure on this site was obtainedThe systems it goes into, and the parts beside it.
Bus protocol, common-mode range, fault exposure and ESD tests.
- VehiclesThe CAN-FD and RS-485 link at every node on the vehicle bus.
- On nearly every boardShips with every node on every industrial bus, including harsh wiring harnesses.
Parts beside it
Read the source behind every figure.
Each document opens inside the site at the cited section; the PDF is the edition of record.
Design files
Bring the socket. We will tell you what SKU-5 has to prove for it.
Send the platform, voltage and power environment, interfaces and qualification needs. The reply names what is architecture, what is evidence and what would have to be tested.