Six functional groups.
A fixed safety core.
The DG32-LITE die is organised into six regions. Five are configurable per SKU. The safety core is closed until silicon test, because the part that catches a fault is the part that cannot be allowed to change.
Drag the die to rotate it. Scroll to walk the regions.
SAFE FROZEN
Safety core
Lockstep pair, fault latch, windowed watchdog
Lockstep CPU pair
MAIN runs the application; CHECKER runs the same instructions two cycles later on mirrored inputs and bus responses.
Comparator and fault latch
Compares every committed store; the first mismatch sets a sticky latch with its cause and drives FAULT_N.
Supervisor and windowed watchdog
Two supply-good inputs with deglitching and reset sequencing, plus a watchdog that faults on a kick that is too early or too late.
WHY Motor control drives power electronics. A silent CPU fault can destroy a bridge; a second core that must agree bit-for-bit turns that fault into an observable signal.
MEMCONFIGURABLE
Memory & boot
64 KB ROM, 32 KB SRAM, QSPI flash
Boot ROM
64 KB of mask-programmed logic that prints a banner, checks the flash image, copies it into SRAM and jumps to it.
Dual-port SRAM
32 KB on 16 macros: one port for CPU and DMA data, the other dedicated to instruction fetch.
QSPI controller
Maps external NOR flash and PSRAM into memory as a data window.
WHY A flash-less die keeps the 130 nm process simple. The cost is loading at boot instead of executing in place; embedded flash is on the roadmap.
MTRCONFIGURABLE
Motor drive
3-phase PWM, DShot × 4, timers
3-phase PWM
Centre-aligned complementary outputs on six gate pins, programmable dead-time up to 5.1 µs, shadow duty registers and an ADC sample trigger.
DShot × 4
Encodes digital ESC frames for four channels onto the PWM pads.
Timers × 2
Two 32-bit timers with compare interrupts.
WHY A firmware brake is only as fast as the loop. A bridge fault needs the safe state now, so the brake path goes straight to the gates.
SNSCONFIGURABLE
Sensing & math
Encoder + Hall, SAR ADC, CORDIC
Encoder and Hall decode
Quadrature A/B/Z with index and three Hall inputs, with edge timestamps.
SAR ADC
8-bit differential converter at ~200 kSa/s, fired by the PWM.
CORDIC
sin/cos, atan2 and magnitude in a fixed 53–58 cycles per operation.
WHY An external SPI ADC read costs ~1.9 µs of a ~5 µs loop, the largest single cost. On-die it becomes a start pulse and a poll.
COMCONFIGURABLE
Connectivity
UART × 2, SPI, I²C, QSPI, GPIO
UART × 2
UART0 carries the boot banner and console; UART1 is free for telemetry.
SPI master
Up to 25 MHz, all four modes, 0.64 µs per 16-bit word.
I²C master
7-bit addressing at 100 or 400 kHz with clock stretching and true open-drain pads.
GPIO
General-purpose pins with synchronised inputs and separate set and clear registers.
WHY The set a motor drive needs, done in silicon where timing matters. CAN-FD is a roadmap item.
SYSCONFIGURABLE
Bus, system & test
Two-master bus, interrupts, DMA, JTAG
On-chip bus and error slave
A lightweight AXI-style bus: two masters (CPU first, then DMA), one transaction at a time, every peripheral a 32-bit register slave.
Interrupt controller
16 sources plus a software interrupt, delivered identically to both cores.
DMA
A second bus master that moves memory blocks without CPU copy loops.
System control
Part ID, pin multiplexing and eight software clock gates for idle peripherals.
Test access
A JTAG port reaching 13 internal scan chains for production test.
WHY There is no debugger halt on this die. A hung bus would be a brick, so every bad access has to be visible and survivable.
SAFE FROZEN
Peripherals change per customer.
The lockstep safety core does not.
Motor control drives power electronics. A silent CPU fault can destroy a bridge; a second core that must agree bit-for-bit turns that fault into an observable signal.
- Lockstep CPU pairMAIN runs the application; CHECKER runs the same instructions two cycles later on mirrored inputs and bus responses.
- Comparator and fault latchCompares every committed store; the first mismatch sets a sticky latch with its cause and drives FAULT_N.
- Supervisor and windowed watchdogTwo supply-good inputs with deglitching and reset sequencing, plus a watchdog that faults on a kick that is too early or too late.
Pre-silicon. The die image is an illustrative model, not a mask layout, and the figures above are design values verified in simulation and static timing.
DG32 physical design.
Silicon validation comes next.
The DeepGrid Silicon Engine capture shows the DG32-LITE layout. It records pre-silicon design work; manufactured-silicon measurements and product qualification are separate milestones.
Inspect the complete layout image