Eleven mature-node products and the separate D100 programme address different equipment needs. Compare the function, what it could replace and what remains to be proven before adoption.
Pre-silicon: every figure on a tile is a design target. Open a tile for its three deciding figures and its film.
SKU-1 · 130 nm BCD
One chip runs the motor and controls its supply up to 120 V.
DG32-LITE: two RISC-V cores in hardware lockstep, the motor-drive peripherals and the FOC maths, at 50 MHz.
Motor control drives power electronics, and a silent CPU fault can destroy a bridge. Hardware lockstep has lived in automotive MCUs such as Infineon AURIX, NXP S32K and TI Hercules; DG32-LITE brings it to the entry-level motor-control tier.
| Question | Software self-test | DG32 hardware lockstep |
|---|---|---|
| When it checks | Periodically, when the test is scheduled | On every committed store |
| Between checks | Blind: a fault can act before the next run | No gap: CHECKER runs two cycles behind |
| Who stops the bridge | Firmware, once it notices | FAULT_N, in hardware, without waiting for firmware |
The 39-cycle figure is measured in simulation, from an injected fault to the latch.
Choose a block to see what it does and why it is there. Then switch to DG32-2DOM: the six groups are the same design from the same source, and only the attention engine and its bridges are new.
50 MHz control domain
SAFE
WhyMotor control drives power electronics. A silent CPU fault can destroy a bridge; a second core that must agree bit-for-bit turns that fault into an observable signal.
Open the full DG32-LITE diagram| Area | DG32-LITE | DG32-2DOM |
|---|---|---|
| Control core | Two RV32IM cores in hardware lockstep | Identical, frozen and unchanged |
| Boot and memory | 64 KB boot ROM, 32 KB dual-port SRAM, external QSPI flash | Identical |
| Motor and sensing | PWM with brake, 4 × DShot, encoder and Hall, SAR ADC, CORDIC | Identical |
| Connectivity | 2 × UART, SPI, I²C, GPIO, JTAG and scan | Identical |
| Control-loop budget | ~300 hardware cycles per loop; ~100 kHz simulated ceiling | Identical; the engine cannot extend it |
| Clocks | One 50 MHz domain | 50 MHz control domain plus a 114 MHz compute domain |
| On-chip compute | None | INT8 attention engine, bit-exact to the software model |
| Package and pinout | QFN-64, 9 × 9 mm, 44 signal pins | Identical; the engine adds no pads |
| Supplies | 1.8 V core, 3.3 V I/O | Identical |
| Power estimate | ~0.43 W at 50 MHz (tool estimate) | Same figure stated; no separate engine figure yet |
| Die | 2.9 × 4.5 mm core block | Its own 3.4 × 4.5 mm die |
| Status | Pre-silicon; dated shuttle plan in source | Design complete, in physical trials |
First silicon · September 2026 multi-project shuttle
Design complete · in physical trials
Pre-silicon. Figures are design values verified in simulation and static timing, not measurements on fabricated parts, unless marked otherwise. The ~0.43 W power figure is a vectorless tool estimate at 25 °C and 1.8 V.
Sampling, the Park transforms and the PWM update are dedicated blocks costing about 300 cycles at any loop rate; the CPU keeps only the two PI regulators. What is left at each rate is the firmware budget.
Cycle costs measured in simulation at the 50 MHz clock; 100 kHz is the simulated ceiling, not a bench result.
Sub-10 nm silicon cannot withstand 28 V to 120 V transient rails, carries no 24-bit high-dynamic-range analog front end, and does not survive automotive and military screening from −55 °C to +125 °C without external support. DeepGrid anchors those physical interfaces on 130 nm and 180 nm, taking the satellite sockets around the sub-10 nm central compute rather than competing with it. DG32 is SKU-4 of that portfolio, the lockstep safety MCU.
| SKU | Part | Node |
|---|---|---|
| SKU-1 | BLDC Motor Controller | 130 nm BCD |
| SKU-2 | Smart-Meter SoC | 130 nm CMOS |
| SKU-3 | High-Reliability PMIC | 180 nm BCD |
| SKU-4 | DG32-LITE | 130 nm CMOS |
| SKU-4 variant | DG32-2DOM | 130 nm CMOS |
| SKU-5 | Robust Transceiver | 130 nm HV |
| SKU-6 | Voltage Supervisor | 180 nm CMOS |
| SKU-7 | DG-RADAR-77 | 0.13 µm SiGe BiCMOS |
| SKU-8 | DG-DISP-17 | 130 nm HV CMOS |
| SKU-9 | DG-SDV-ZONE | 130 nm CMOS and BCD |
| SKU-10 | DG32-Max | 130 nm CMOS (SKY130) |
| SKU-11 | DG-BMS-SOH | 130 nm CMOS (SKY130) |
| Track B | DG-D100 | 28 nm; failsafe island buildable at 130 nm |
Portfolio, numbering and nodes follow the SKU Blueprint, October 2026. Phase names the sovereignty foundry, not a date: Phase 1 SkyWater, Phase 2 IHP, Phase 3 SCL Mohali. Anchor customers and contract values are held off this table pending verification.
For a drive that needs hardware lockstep safety, hardware FOC acceleration and native DShot in a 64-pin part.
WHYIt is pre-silicon. Bring-up must measure loop costs, fault latency, timing and electrical behaviour before design values become silicon results.
For a drive that should also watch its own motor: bearing-fault or anomaly detection on phase-current data, without a second processor.
WHYThe engine runs on its own clock behind bridges, so condition monitoring cannot extend the control core’s worst-case execution time. Design complete, in physical trials.
