SKU-8 · 130 nm high-voltage CMOS Rugged display driver
SKU-8 drives 1280 columns at up to 12 V and flags a frozen image within two frames.
Every figure on this page is a design target unless marked otherwise.
- Output swing
- 0 to 12 V; 24 V gate level shift
- Column outputs
- 1280 × 10-bit DACs with charge-sharing precharge (about 40% less drive power)
- Safety
- Frame-freeze self-test, alert within two frames
SKU-8 drives 1280 columns at up to 12 V and flags a frozen image within two frames.
SKU-8 targets rugged displays, combining panel-driving functions with detection of a frozen image.
- Job
- Translate digital image data into panel drive signals.
- Replaces
- Imported timing-controller and column-driver chipsets in rugged and industrial displays.
- Status
- RTL ready for the digital logic; high-voltage column amplifiers designed and simulated. Layout and silicon proof follow on the first prototype.
The business case for SKU-8
Evaluate readability and failure indication as part of the operator’s task, not simply as display specifications.
What it replaces
Imported timing-controller and column-driver chipsets in rugged and industrial displays.
Customer opportunity
Rugged and industrial display makers; the cockpit version serves avionics displays.
Policy and demand
The defence procurement list names a 17-inch rugged SXGA display from BEL, due December 2027.
The delivery trade-off
Panel columns need a 0–12 V swing, a high-voltage, thick-oxide job that mature nodes do best.
What SKU-8 claims, what it is worth, and what gates it.
The following mechanisms explain the proposed customer benefit. Each still needs to be validated in the complete product.
SKU-8 drives 1280 columns at up to 12 V and flags a frozen image within two frames.
SKU-8 targets rugged displays, combining panel-driving functions with detection of a frozen image.
A frozen image raises an alert within two frames.
Evaluate readability and failure indication as part of the operator’s task, not simply as display specifications.
Readability and the freeze alert need tests on the target panel.
Panel compatibility, environmental performance and fault indication need system tests.
Architecture targets, not datasheet values.
Every figure is a design target stated in the SKU Blueprint, page 31. None is a measurement of manufactured silicon.
- 12 VColumn output swing
- 14-bitTemperature-fed gamma
- 2 framesFreeze alert
Detailed architecture and specifications
- Process
- 130 nm high-voltage CMOS
- Resolution
- SXGA 1280 × 1024 at 60 Hz; WXGA and Full HD variants
- Column outputs
- 1280 × 10-bit DACs with charge-sharing precharge (about 40% less drive power)
- Output swing
- 0 to 12 V; 24 V gate level shift
- Inputs
- Dual LVDS, MIPI DSI, parallel RGB
- Gamma
- 14-bit table with temperature feedback
- Safety
- Frame-freeze self-test, alert within two frames
- Process
- 130 nm high-voltage CMOS
- Maturity
- Architecture scope
- Designed toward
- ISO 26262 ASIL-B · MIL-STD-810G · DEF-STAN 00-35
- Source
- SKU Blueprint, October 2026, page 31
Standards the architecture is designed toward. No DeepGrid part holds a certification or qualification today.
System architecture, signal flow and engineering references
Marker ①: Video enters over LVDS or MIPI DSI into a line buffer
A frame arrives at Video input through LVDS RX, a dual link at 655 Mbps per lane, through four-lane DSI RX, or as parallel RGB. Both receivers write the Line buffer, dual-port SRAM holding four lines of 1280 pixels at 24 bits, which decouples the incoming link from the pace of the pixel pipeline.
Video input
Marker ②: The pipeline corrects every pixel for panel temperature
The Line buffer feeds the Pixel pipeline at 24 bits per pixel. De-gamma linearises the input, Colour applies a 3 × 3 matrix with white point, and the Gamma LUT maps it through a 14-bit table with temperature feedback from an on-die sensor. LCD response shifts with heat, and this is how contrast holds at +85 °C in direct sun.
Video inputPixel pipeline
Marker ③: Dithered pixels set one 10-bit DAC per column
Dither applies temporal and spatial dithering, then the pixels cross the control bus to the Column (source) drivers. The DAC bank holds one 10-bit resistor-string DAC with a buffer for each column, 1280 in all. Here the digital half of the die hands over to the high-voltage half.
Pixel pipelineColumn (source) drivers · high-voltage
Marker ④: High-voltage amps swing 3,840 outputs from 0 to 12 V
Output amps are rail-to-rail high-voltage amplifiers on thick oxide, swinging 0 to 12 V, a range dense nodes cannot reach. They drive Column outputs × 1280: three sub-pixels per column, 3,840 outputs. Charge-sharing precharge between adjacent columns cuts drive power by about 40%.
Column (source) drivers · high-voltage
Marker ⑤: The timing controller scans the rows at up to 24 V
Timing + test sets the frame. The TCON generates horizontal and vertical timing with programmable porches from a 100 MHz pixel-clock PLL, and scans the rows through the Gate driver IF in Row + backlight with a level shift up to 24 V. VCOM drives the common electrode, and Backlight runs the LED string across eight local-dimming zones.
Timing + testRow + backlight
Hardware notices a frozen picture within two frames
BIST + safety in Timing + test compares a CRC of each frame with the one before, in hardware. If the image stops updating, it alerts the operator within two frames instead of leaving a stale picture on a cockpit screen. Test pattern adds colour bars for checking the drive path to the panel.
Timing + test
Numbered markers
- ①Marker ①: Video arrives over LVDS, MIPI DSI or parallel RGB.
- ②Marker ②: The line buffer feeds the pixel pipeline, 24 bits per pixel.
- ③Marker ③: Dithered pixels drive the column DACs.
- ④Marker ④: High-voltage amplifiers drive the 3,840 column outputs.
- ⑤Marker ⑤: The timing controller scans the rows through the gate driver.
Block responsibilities
- Video input
Dual-link LVDS at 655 Mbps per lane and four-lane MIPI DSI receivers into a dual-port line buffer of four 1280-pixel, 24-bit lines.
Guide: Video input- Pixel pipeline
De-gamma, a 3 × 3 colour matrix with white point, a 14-bit gamma table with temperature feedback, and temporal and spatial dithering.
Why LCD response shifts with panel temperature, so the gamma is temperature-compensated.
Guide: Pixel pipeline- Timing + test
A timing controller with programmable porches, a 100 MHz pixel-clock PLL, a colour-bar test pattern and frame-freeze detection that alerts within two frames.
Guide: Timing + test- Column (source) drivers · high-voltage
One 10-bit resistor-string DAC per column and rail-to-rail high-voltage amplifiers swinging 0 to 12 V, driving 3,840 sub-pixel outputs with charge-sharing precharge.
Why A 0 to 12 V swing on thick oxide is mature-node territory; precharge cuts driver power by about 40%.
Guide: Column (source) drivers · high-voltage- Row + backlight
A gate-driver interface with a 24 V level shift, the VCOM electrode, an LED backlight with eight local-dimming zones, and ambient light and temperature sensing.
Guide: Row + backlight
Primary sources
- SKU-8 architecture guideEvery block group, the data flows and the design targets.Opens in the site
- SKU Blueprint, October 2026SKU-8: what it replaces, who uses it, its status and its architecture diagram.PDF · 46 pages
2 integration and validation references
- LVDS Owner’s Manual (TI SNLA187)How LVDS links carry video, and their timing and termination.Texas Instruments · PDF
- MIPI DSI specification overviewThe display serial interface on the second receiver.MIPI Alliance
Background reading explains the general technique each block uses. None of it describes this part or implies its certification.
Architecture from the SKU Blueprint, page 31. A functional view, not a floorplan.
7 questions SKU-8 has to answer before it can be relied on.
The Blueprint’s design and status notes raise these. Each is a question silicon, test or layout has to answer before SKU-8 can be relied on.
Panel columns swing 0 to 12 V and row drivers need 24 V.Physics
Thick-oxide high-voltage amplifiers and level shifters on a 130 nm HV process; dense nodes cannot reach these voltages.
Contrast must hold at +85 °C in direct sun.Physics
An on-die temperature sensor feeding a 14-bit gamma table.
A frozen display in a vehicle, cockpit or control room is a hazard, not a glitch.Physics
Frame-by-frame CRC comparison in hardware.
Why 130 nmOpen
Which voltages force the driver onto a high-voltage process rather than a dense digital one?
Charge sharingOpen
How much energy does precharge between adjacent columns recover during full-screen video?
Freeze detectionOpen
How do successive frame CRCs alert the operator within two frames if the image stops updating?
Heat and contrastOpen
How does the gamma table track temperature to hold contrast at +85 °C?
An architecture, with its evidence named.
- Strongest evidence
- Architecture diagram and status in the SKU Blueprint.
- Development status
- RTL ready for the digital logic; high-voltage column amplifiers designed and simulated. Layout and silicon proof follow on the first prototype.
Rugged display applications and safety requirements are targets, not certifications.
How every figure on this site was obtainedThe systems it goes into, and the parts beside it.
Panel interface, resolution, column voltage and environmental tests.
- Defence, avionics and dronesRugged and industrial displays; a wider-temperature version for cockpits.
- On nearly every boardIndustrial control panels, rail passenger displays and automotive instrument clusters.
Parts beside it
Read the source behind every figure.
Each document opens inside the site at the cited section; the PDF is the edition of record.
Design files
Bring the socket. We will tell you what SKU-8 has to prove for it.
Send the platform, voltage and power environment, interfaces and qualification needs. The reply names what is architecture, what is evidence and what would have to be tested.