Start with the OEM socket.
Agree voltage, signal quality, interfaces, package, environmental conditions and qualification evidence. A reusable digital block cannot erase those physical constraints.
One RISC-V platform and verification flow, reused across eleven mature-node chips.
DeepGrid’s mature-node strategy connects motion, power, sensing, interfaces and safety to the needs of equipment makers. DG32 is the detailed pre-silicon engineering case; the wider portfolio remains a set of individually scoped architectures.
Shared digital foundation
Reusable RISC-V IP and verified digital logic
Reuse implementation methods and digital building blocks across the portfolio.
Motor power stageSpecialist physical requirements
Analog acquisitionSpecialist physical requirements
Physical interfacesSpecialist physical requirements
RF sensingSpecialist physical requirements
Proposed integration
Organic-substrate SiP
Combine suitable dies and processes in a package. This is a portfolio concept; DG32 uses its own QFN-64 package.
Digital IP carries from chip to chip; voltage, noise, RF and screening are engineered per socket.
A shared processor, tools and verification flow make the second chip cheaper than the first. Voltage, noise, radio frequency and screening do not transfer: each socket sets its own physics, and those blocks are engineered for it.
Reusable digital IP across the portfolio
- Processor and digital building blocks
A common RISC-V foundation and reusable digital IP can serve multiple product architectures.
Reuse does not make every chip the same implementation, frequency or safety configuration.
Mature-Node Silicon System Architecture · §5: Canonical Processor Architecture - Shared silicon development capability
In-house engineering, open-source tools and shared MPW fabrication are the development method.
A reusable flow is not an achieved cost multiplier or a guaranteed turnaround.
Mature-Node Silicon System Architecture · §§2–3
Power, RF and packaging need product-specific engineering
- Power and analog
References, converters, high-voltage devices and protection structures must meet the socket’s physical requirements.
Analog and high-voltage work can require additional silicon cycles.
Mature-Node Silicon System Architecture · §3: Two-Speed Development Reality - RF and exposed interfaces
Radar RF uses a SiGe front end; harness interfaces require their own fault and ESD protection.
Digital IP portability does not establish analog or RF portability.
SKU Architecture Compendium · §2, Sheets 6 and 8; §3.3 - Proposed organic-substrate integration
The SiP concept uses a four-layer organic BT-resin, 15 × 15 mm BGA package; a later compute die would join by flip-chip.
A proposed multi-die architecture, distinct from DG32’s 9 × 9 mm QFN-64. Package qualification remains separate.
SKU Architecture Compendium · §3.5: Sheet 13
Every chip is cut from DG SDV: secure, safe, host and accelerator domains on one interconnect.
DG SDV is the architecture the portfolio is drawn from: secure, safe, host and accelerator domains on one regulated interconnect. Each product takes the part of it its socket needs.
- Secure domainDual-lockstep RV32 cores, hardware cryptography, OTP and boot ROM, its own always-on power.
- Safe domainTriple-core lockstep real-time cores with private ECC memories.
- Host domainMulti-core 64-bit RISC-V running Linux, with MMU and floating point.
- AcceleratorsVector and integer clusters on interleaved scratchpad memory.
- InterconnectA 64-bit AXI4 matrix with bandwidth regulation, so the host cannot starve the safe domain.
The products are scaled-down instances of this reference: SKU-4 carries a two-core version of the safe domain, SKU-9 adds the secure domain at the vehicle zone, and D100 brings the host and accelerators onto a drone. The platform itself is an architecture, not a product, and its safety and security levels are design targets.
DG SDV architectureDeepGrid sells through equipment makers: boxes, not chips.
The whitepaper’s “boxes, not chips” strategy works through equipment makers and their assemblies or LRUs. It is a proposed commercial route, not proof of contracted demand, legal procurement eligibility or qualified production.
Separate opportunity from commitment.
Architecture breadth, forecasts and a possible procurement route are not customer orders. Evaluation needs named requirements and decision gates.
A chip takes 198 days in the model: 30 digital, 168 physical.
The 198-day model allocates 30 digital and 168 physical days. It is analytic planning; analogue and high-voltage programmes may need extra silicon cycles.
- 01
Design
Architecture, requirements and review records
- 02
Logic verification and timing closure
RTL verification and physical implementation reports
- 03
MPW fabrication
Fabrication records and returned silicon
- 04
Bring-up
Board measurements and functional test results
- 05
Characterisation
Electrical limits across conditions
- 06
Qualification
Reliability, safety and application evidence
Four named conditions would change the roadmap.
Scale selected logic. Preserve the physical job.
- 130 / 180 nmPhysical foundation
- Selective scalingSuitable logic blocks
- 28 nmIntended compute
Analog, power and RF requirements continue to govern their own blocks.
Build a route to manufacturing resilience.
- SkyWater 130Open process route
- IHP SG13G2Specialist RF route
- SCL 180Intended route
Distinct process and qualification plans, not interchangeable qualified fabs.
Four conditions that change the plan
S1No binding Ripple Metering letter by the Chip 2 factory-order cutoff.
Pause Chip 2 for one cycle and reallocate its capital to Chips 1 and 3.
S2Chip 6 fails military screening twice.
Defer all forward defence revenue projections by 12 months, updating materials within 30 days.
S3At the FY29 review, delivered Chinese component prices fall below bare manufacturing cost.
Exit ceiling-fan drivers and focus on two-wheelers and proprietary modules.
S4SCL Mohali slips by more than two manufacturing cycles.
Disclose the delay and use the SkyWater and IHP routes for production plans.
An evaluation starts with one customer programme.
DG32 physical design.
Silicon validation comes next.
The DeepGrid Silicon Engine capture shows the DG32-LITE layout. It records pre-silicon design work; manufactured-silicon measurements and product qualification are separate milestones.
Inspect the complete layout image