DG32 validation is pre-silicon; qualification remains ahead.
Design studies, simulation, prototypes and measured silicon support different decisions. This register helps separate an opportunity worth evaluating from a product ready for deployment.
DG32 physical design.
Silicon validation comes next.
The DeepGrid Silicon Engine capture shows the DG32-LITE layout. It records pre-silicon design work; manufactured-silicon measurements and product qualification are separate milestones.
Inspect the complete layout image
DG32 performance remains pre-silicon; measured operating limits are pending.
No measured silicon results are published. Dated shuttle plans do not establish returned silicon or completed bring-up.
Until then, each of the 16 load-bearing figures on this site is one of five kinds of evidence, or a design decision that measures nothing. They are different kinds, not steps on a ladder, and each one below lists the figures that rest on it.
The applications page places DG32 among twelve chips. The other eleven have no silicon at all yet, so the last section says what each of them rests on instead.
Three unsupported performance claims are excluded from product evaluation.
The source documents carry figures this site leaves out. Each was checked and found wrong in a way that matters, so it is printed here with the reason rather than quietly dropped.
- ₹1.01 Cr contracted, Indian Army MCEME, attached to Chip 4Verification found it materially misdescribed: ₹23.01L delivered, ₹78.39L is L1 (lowest bidder, not an award), and it sits in Deepgrid Datacentre Pvt Ltd rather than Deepgrid Semi, with MCEME-owned IP.
- 39.3 TOPS measured on FPGAA derivation, not a measurement. The Artix-7 board ceilings near 1.8 TOPS.
- 12.9× cheaper than MobileyeCategory error: their ASP against our die cost. Loaded with NRE at plan volumes the advantage is about 2.3×.
Simulated
Simulation shows the design behaves as intended before any silicon exists.
Measured in simulation of the design as built. It shows the logic does what it should. A bench measurement on first silicon is what confirms it.
“This is the safety core. MAIN runs the application. CHECKER runs the same instructions two cycles later, on the same inputs, and the comparator checks every committed store. On a mismatch, the first cause is latched and FAULT_N goes low. Route that pin to the gate-driver enable, and the bridge turns off in hardware, without waiting for firmware.”
DG32-LITE architecture film · slide 6 · 2:33–2:59| Figure | What it measures | Source |
|---|---|---|
| 39 cycles | Injected fault to FAULT_N asserted and the PWM bridge disabled, with no firmware in the path | DG32-LITE Architecture Guide |
| ~100 kHz | Closed current-loop rate, the simulated ceiling: about 5 µs acquisition plus 5 µs compute | DG32-LITE Architecture Guide |
| ~300 cycles | Fixed hardware cost per loop: one ADC sample, two CORDIC operations and a PWM write, at any loop rate | DG32-LITE Architecture Guide |
| 177 cycles | On-die SAR ADC conversion, fired by the PWM at the current-ripple null | DG32-LITE Architecture Guide |
| 53 to 58 cycles | One CORDIC sin/cos or rotation operation | DG32-LITE Architecture Guide |
| ~8 cycles per instruction | Cost of a CPU instruction on this fetch-bound core, used to convert the cycle budget into instructions | DG32-LITE Architecture Guide |
Post-route
Post-route timing is checked on the laid-out design, which is still not silicon.
Static timing on the placed-and-routed hardened design. It accounts for real wire lengths, but it is still a layout result: the silicon numbers come with bring-up.
“Splitting the clocks worked: both domains close timing after place-and-route, with positive slack. The fifty megahertz control side has zero point three nanoseconds of slack, and the one hundred fourteen megahertz engine side zero point one nine, on a die of three point four by four point five millimetres. Those are layout results, not silicon; the silicon numbers come with bring-up.”
DG32-2DOM architecture film · slide 11 · 4:50–5:17| Figure | What it measures | Source |
|---|---|---|
| 55 to 62 MHz | Maximum frequency of the lockstep core on the placed-and-routed design, which is what sets the 50 MHz clock | DeepGrid Datasheets Engineering Specification |
Analytic
Design and development estimates require validation.
Derived from the architecture, not yet run on a bench. Where a cost is plain arithmetic, it can be worked out before silicon. Nothing has run it yet.
“The engine’s cost can be worked out before silicon, because it is plain arithmetic. At sixteen lanes and four hundred keys, with keys of thirty-two bytes and values of sixty-four, combining the values takes half of each row, about sixteen hundred cycles. Scoring the keys takes a quarter, requantising about seven hundred, and the divide just forty-eight, roughly thirty-two hundred and forty in all. A bench measurement replaces that estimate once first silicon arrives.”
DG32-2DOM architecture film · slide 10 · 4:18–4:50| Figure | What it measures | Source |
|---|---|---|
| 82% | Available DIAGNOSTIC headroom at a 10 kHz FOC rate: core clock cycles left after the hardware datapath AND the control firmware. Not the same quantity as the cycle budget, which is the period minus the fixed hardware cost alone and is 94% at the same rate. | DG32 AI Architecture |
| 198 days | RTL to GDSII shuttle loop on the verified SkyWater factory calendar | Mature-Node Silicon System Architecture |
Tool estimate
Power consumption awaits first-silicon measurement.
A vectorless power estimate from the implementation tools. The implementation tools estimate power without a recorded switching pattern behind it. It is not a measured figure.
“Power is simple. All logic, memory and the ADC draw from the one point eight volt user rail. The other user rails are unused, and are tied to their nominal voltage only to keep protection structures biased. Bring up three point three volts before or together with one point eight. The tool estimate is about zero point four three watts at fifty megahertz.”
DG32-LITE datasheet film · slide 7 · 2:48–3:15| Figure | What it measures | Source |
|---|---|---|
| ~0.43 W | Vectorless power estimate at 50 MHz, 25 °C and 1.8 V, from the implementation tools | DeepGrid Datasheets Engineering Specification |
Process nominal
Electrical limits are process nominals until first-silicon characterisation replaces them.
The 130 nm process limits for each supply domain. Every electrical limit in the datasheet is a design target or a process nominal, and first-silicon characterisation will replace it.
“Every electrical limit in this datasheet is a design target or a process nominal, and first-silicon characterisation will replace it. The core supply runs from one point seven one to one point eight nine volts, and the input and output supply from three to three point six. The analog inputs accept zero to one point eight volts, and absolute maximums sit just above the operating range.”
DG32-LITE datasheet film · slide 6 · 2:20–2:48| Figure | What it measures | Source |
|---|---|---|
| 130 nm | Process node. Chosen so the die can take 28 to 120 V transient rails and survive −55 to +125 °C, which sub-10 nm cannot | Mature-Node Silicon System Architecture |
Pin count, memory capacity and clock targets define the architecture.
A pin count or a memory size is chosen, not measured, so it carries no evidence kind. Labelling it “Simulated” would cheapen the word.
| Figure | What it measures | Source |
|---|---|---|
| ISO 26262 ASIL-D | The target the lockstep safety MCU is designed against. A mechanism, not a held certificate | Mature-Node Silicon System Architecture |
| 64 KB boot ROM | Mask-programmed boot path. Built as logic rather than a memory macro | DeepGrid Datasheets Engineering Specification |
| 32 KB SRAM | Dual-port, on 16 macros: one port for CPU and DMA data, the other for instruction fetch | DeepGrid Datasheets Engineering Specification |
| QFN-64, 9 × 9 mm | Package: 44 signal pins and 20 supply and ground pins, identical on both parts | DeepGrid Datasheets Engineering Specification |
| SKU-4 | DG32-LITE’s place in the portfolio: SKU-4, the lockstep MCU | SKU Blueprint, October 2026 |
The rest of the portfolio
The other eleven chips rest on design documents, RTL and FPGA prototypes, not silicon.
Where they go and what they replace are on the applications page, from the SKU Blueprint. None has been fabricated. Four have named logic running as circuit code on an FPGA, which the whitepaper counts as designed rather than done: 81.25 MHz is, in its words, “a limit of the FPGA, not of our design”. The rest are architecture designs.
| Chip | Strongest evidence today | Next step | Source |
|---|---|---|---|
| BLDC motor controllerSKU-1 | FPGA-validated: the motor control datapath runs as circuit code on an Artix-7 at 81.25 MHz. | RTL ready; analog gate-drive and sensing circuits designed and simulated. First multi-project wafer run, cycle 1; a cost-down cut for fans and appliances is a second tape-out on the same RTL. | Whitepaper v3, §3 |
| Smart-meter SoCSKU-2 | FPGA-validated: the meter measurement chain runs as circuit code on the same Artix-7. | RTL ready and FPGA-validated; the six-channel analog front end is designed and simulated. Cycle-1 wafer run, alongside SKU-1. | Whitepaper v3, §3 |
| High-reliability power ICSKU-3 | Architecture diagram in the SKU Blueprint; prototyping planned on sky130 20 V devices, production at SCL 180 nm. | RTL ready for the digital sequencer and telemetry; analog power circuits designed and simulated. The sky130 prototype tests the control logic and low-voltage rails; the 28 V front end and power stage arrive on SCL 180 nm. | SKU Blueprint, p. 16 |
| RS-485 and CAN-FD transceiverSKU-5 | Architecture diagram and status in the SKU Blueprint. | RTL ready for the digital logic; analog line drivers designed and simulated. Prototype on the December 2026 shuttle; layout and silicon proof follow. | SKU Blueprint, p. 22 |
| Voltage supervisorSKU-6 | FPGA-validated: the supervisor sensing chain runs as circuit code on the same Artix-7. | RTL ready for the digital logic; comparators and reference designed and simulated. Prototype on sky130, production on SCL 180 nm. | Whitepaper v3, §3 |
| 77 GHz 4D radarSKU-7 | Architecture diagram and status in the SKU Blueprint. The SiGe front end has no FPGA equivalent, so it is proven on silicon or not at all. | RTL ready for the CMOS signal-processing chip, validated on FPGA. The SiGe front end can only be proven on silicon, on IHP SG13G2. | SKU Blueprint, p. 28 |
| Rugged display driverSKU-8 | Architecture diagram and status in the SKU Blueprint. | RTL ready for the digital logic; high-voltage column amplifiers designed and simulated. Layout and silicon proof follow on the first prototype. | SKU Blueprint, p. 31 |
| Zonal gatewaySKU-9 | Architecture diagram and status in the SKU Blueprint. | RTL ready; prototype on the December 2026 shuttle, a 130 nm chip at 100 MHz. | SKU Blueprint, p. 34 |
| DG32-Max secure microcontrollerSKU-10 | RTL feature-complete; every bench and firmware test passes, including secure boot on all three test images. No silicon result yet. | RTL feature-complete on 1 October 2026; FPGA proof and place-and-route for the December 2026 OpenFrame shuttle follow. | SKU Blueprint, p. 37 |
| SOH-aware battery-management controllerSKU-11 | Block specification: twenty blocks in six groups, reusing the feature-complete DG32-Max platform RTL. | Block specification issued September 2026; no wafer-run slot assigned yet. | SKU Blueprint, p. 40 |
| D100 drone SoCD100 | FPGA-validated: the drone position engine runs as circuit code on the same Artix-7. | Track B: funded by a separate round once the eleven mature-node chips earn revenue; its lockstep safety core is shared with SKU-4. | Whitepaper v3, §3 |
Product maturity, qualification limits and evaluation requirements.
- No functional-safety certification. Hardware lockstep is a mechanism, not a certificate.
- No sign-off result for the tape-in die: the four gates it must pass are listed, not reported as passed.
- No price or cost claims against any competitor.
- No silicon result for the other eleven chips: they rest on architecture designs, RTL and logic validated on an FPGA; nine prototypes are planned for the December 2026 shuttle (SKU Blueprint, October 2026). The one DeepGrid chip returned so far is a 130 nm test chip made on its own flow (whitepaper v3, §3).
- No market size or price for the wider portfolio: the Blueprint’s market estimates are internal planning figures and are not shown. The only revenue figures on this site are plan targets, on the Portfolio strategy and Business plan pages; they are not results.
Every figure above was located in its source document, and a build gate re-runs that search and fails when a source stops carrying a figure.