SKU-2 · 130 nm CMOS Smart-meter SoC
SKU-2 meters energy to Class 0.5S and keeps the tamper record on an always-on domain under 2 µW.
Every figure on this page is a design target unless marked otherwise.
- Front end
- Six-channel 24-bit sigma-delta, sinc³ OSR 256
- Accuracy class
- Class 0.5S target (P, Q, S, THD to 15th harmonic)
- Always-on domain
- Under 2 µW, 32.768 kHz, 2.2 to 3.6 V backup
SKU-2 meters energy to Class 0.5S and keeps the tamper record on an always-on domain under 2 µW.
SKU-2 brings energy measurement, meter control and outage records together for utilities and meter makers.
- Job
- Measure electrical energy and preserve metering state when mains power is absent.
- Replaces
- An ADE9153 or V9203-class metering front end plus a separate meter MCU: one chip instead of two.
- Status
- RTL ready and FPGA-validated; the six-channel analog front end is designed and simulated. Cycle-1 wafer run, alongside SKU-1.
The business case for SKU-2
The commercial test is whether the meter meets the tender’s accuracy, tamper and service requirements.
What it replaces
An ADE9153 or V9203-class metering front end plus a separate meter MCU: one chip instead of two.
Customer opportunity
Household meters; transformer, feeder and commercial meters; rooftop-solar net meters; EV chargers; building submeters.
Policy and demand
Tamper detection is a tender requirement, which makes it a silicon differentiator. RDSS funds the national prepaid smart-meter rollout, PM Surya Ghar adds a net meter to every rooftop-solar home, and every public EV charger bills by energy.
The delivery trade-off
A 24-bit sigma-delta converter needs precision poly resistors, MiM capacitors and real device matching. 130 nm has all three; fine nodes trade them away.
What SKU-2 claims, what it is worth, and what gates it.
The following mechanisms explain the proposed customer benefit. Each still needs to be validated in the complete product.
SKU-2 meters energy to Class 0.5S and keeps the tamper record on an always-on domain under 2 µW.
SKU-2 brings energy measurement, meter control and outage records together for utilities and meter makers.
A meter needs one chip for measurement, security and its own time base.
The commercial test is whether the meter meets the tender’s accuracy, tamper and service requirements.
The metrology chain is FPGA-validated; Class 0.5S accuracy is not yet measured.
Accuracy and outage behaviour need measured evidence before a utility deployment.
Architecture targets, not datasheet values.
Every figure is a design target stated in the SKU Blueprint, page 13. None is a measurement of manufactured silicon.
- 24-bitSix-channel sigma-delta front end
- 0.5SAccuracy class
- < 2 µWAlways-on domain
Detailed architecture and specifications
- Process
- 130 nm CMOS
- Front end
- Six-channel 24-bit sigma-delta, sinc³ OSR 256
- Accuracy class
- Class 0.5S target (P, Q, S, THD to 15th harmonic)
- Processor
- DGridRiscV at 100 MHz, AHB-Lite multilayer bus
- Always-on domain
- Under 2 µW, 32.768 kHz, 2.2 to 3.6 V backup
- Security
- AES-256, SHA, secure boot, tamper key erase
- Interfaces
- DLMS/COSEM UART, 4 × 40 segment LCD, optical port
- Process
- 130 nm CMOS
- Maturity
- Architecture scope
- Designed toward
- IEC metering accuracy Class 0.5S
- Source
- SKU Blueprint, October 2026, page 13
Standards the architecture is designed toward. No DeepGrid part holds a certification or qualification today.
System architecture, signal flow and engineering references
Marker ①: Six sense channels enter one 24-bit front end
Voltage and current from the V / I sense inputs, six channels in all, enter DG-AFE6 in the Metrology zone: six 24-bit sigma-delta converters. The converter sets billing accuracy, so it is dedicated hardware with low flicker noise and stable references, calibrated once. The design is developed toward Class 0.5S across a 1000:1 current range.
Metrology
Marker ②: DECIM turns the raw bit stream into clean samples
DECIM filters each 24-bit sigma-delta stream through a sinc³ decimator at an oversampling ratio of 256, so every channel reaches the metrology engine as a clean, lower-rate sample. Doing this in hardware keeps the filtering off the processor and keeps the measurement chain fixed from the sense pin to the energy figure.
Metrology
Marker ③: METRO computes power and harmonics in hardware
METRO turns the samples into the figures a meter bills on: active, reactive and apparent power, P, Q and S, and total harmonic distortion to the 15th harmonic. Billing accuracy depends on the converter and the arithmetic together, which is why both sit in the Metrology zone rather than in firmware on the core.
Metrology
Marker ④: Results cross the bus to be stored and signed
Results cross the 32-bit AHB-Lite multilayer bus to the Compute + security zone. The DGridRiscV core at 100 MHz and the four-channel DMA move and store them, and DG-SE, with AES-256 and SHA-256, protects the record. Secure boot and tamper key erase guard the code and keys the readings depend on.
Compute + security
Marker ⑤: Readings leave the meter on the DLMS/COSEM UART
In the Peripherals row, the UART carries readings out in DLMS/COSEM, the metering protocol. Beside it, the LCD drives a 4 × 40 segment display, the Timer handles capture and compare, and GPIO switches the relay and LED. One die now covers measurement, security and the meter’s own interfaces.
Peripherals
The always-on domain keeps time and tamper state alive
PMU + RTC in the Always-on zone runs from a 32.768 kHz crystal and a 2.2 to 3.6 V backup cell, drawing under 2 µW, isolated from the 100 MHz core. The RTC keeps a tamper log and Tamper watches the case and magnet inputs, so the clock and the tamper record survive when the mains is gone.
Always-onPeripherals
Numbered markers
- ①Marker ①: Six voltage and current channels enter the front end.
- ②Marker ②: The 24-bit samples decimate through sinc³ at OSR 256.
- ③Marker ③: The metrology engine computes P, Q, S and THD.
- ④Marker ④: Results cross the 32-bit bus to the core and DMA.
- ⑤Marker ⑤: Readings leave on the DLMS/COSEM UART.
Block responsibilities
- Metrology
A six-channel 24-bit sigma-delta front end, a sinc³ decimator at OSR 256, and a metrology engine for P, Q, S and THD to the 15th harmonic.
Why Billing accuracy is set by the converter and the arithmetic, so both are dedicated hardware.
Guide: Metrology- Compute + security
A DGridRiscV core, a four-channel DMA and the DG-SE security engine with AES-256 and SHA-256.
Guide: Compute + security- Always-on
A PMU and RTC on a 32.768 kHz crystal with brownout detection, drawing under 2 µW.
Why Time and tamper state must survive when mains power is gone.
Guide: Always-on- Peripherals
Tamper-logging RTC, capture and compare timer, 4 × 40 segment LCD, DLMS/COSEM UART, case and magnet tamper inputs, and GPIO for relay and LED.
Guide: Peripherals
Primary sources
- SKU-2 architecture guideEvery block group, the data flows and the design targets.Opens in the site
- SKU Blueprint, October 2026SKU-2: what it replaces, who uses it, its status and its architecture diagram.PDF · 46 pages
3 integration and validation references
- DLMS User AssociationThe DLMS/COSEM metering protocol the UART speaks.DLMS UA
- RISC-V ratified specificationsThe instruction set the DGridRiscV cores execute.RISC-V International
- Arm AMBA specifications, including AXI and AHBThe bus protocol family the on-chip bus is modelled on.Arm
Background reading explains the general technique each block uses. None of it describes this part or implies its certification.
Architecture from the SKU Blueprint, page 13. A functional view, not a floorplan.
7 questions SKU-2 has to answer before it can be relied on.
The Blueprint’s design and status notes raise these. Each is a question silicon, test or layout has to answer before SKU-2 can be relied on.
Class 0.5S accuracy across a 1000:1 current range.Physics
A sigma-delta converter with low flicker noise and stable references, calibrated once for a long service life.
The clock and tamper log must survive outages on a backup cell.Physics
An isolated always-on domain drawing under 2 µW, separate from the 100 MHz core.
Open 130 nm processes have no embedded flash.Physics
Code lives in ROM, ECC SRAM and encrypted external QSPI, or in SCL non-volatile memory where available.
Accuracy over a lifetimeOpen
How does the front end hold Class 0.5S across a 1000:1 current range without drift over a fifteen-year service life?
Magnetic and DC tamperOpen
When a strong magnet or injected DC tries to defeat metrology, how is the imbalance detected and measurement preserved?
Blackout retentionOpen
What leakage crosses the isolation cells into the always-on domain during a thirty-day outage on the backup cell?
Non-volatile memoryOpen
Which code-storage option ships first: ROM with encrypted QSPI, or SCL non-volatile memory?
An architecture, with its evidence named.
- Strongest evidence
- FPGA-validated: the meter measurement chain runs as circuit code on the same Artix-7.
- Development status
- RTL ready and FPGA-validated; the six-channel analog front end is designed and simulated. Cycle-1 wafer run, alongside SKU-1.
Metrology and low-power figures are architecture targets, not published production measurements.
How every figure on this site was obtainedThe systems it goes into, and the parts beside it.
Accuracy class, analog front end, tamper detection and backup operation.
Parts beside it
Read the source behind every figure.
Each document opens inside the site at the cited section; the PDF is the edition of record.
- SKU Blueprint, October 2026 (11 SKUs + D100)SKU-2, page 13 · source of recordPDF · 46 pages
- Mature-Node Silicon for India’s Defence (Whitepaper v3)Evidence for this partPDF · 71 pages
Design files
Bring the socket. We will tell you what SKU-2 has to prove for it.
Send the platform, voltage and power environment, interfaces and qualification needs. The reply names what is architecture, what is evidence and what would have to be tested.